VCOMISH instruction (AVX10.1)

VCOMISH compares the low half of an XMM register with the low half of another register or a 16-bit memory operand and reports the result in EFLAGS the way VCOMISS does for singles: ZF, PF and CF all set for unordered, CF alone for less, ZF alone for equal, none for greater, and OF, SF and AF cleared. Like it, VCOMISH raises the invalid-operation exception for a NaN of either kind, where VUCOMISH does so only for a signaling NaN, and with that exception unmasked it faults without changing EFLAGS. It writes no register, so it takes no write mask; {sae} suppresses the exception. The encoding is EVEX map 5, opcode 2Fh, that of COMISS, with EVEX.vvvv required to be 1111b; VADDPH covers the format and the CPUID bits.

In our builds

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles a < b and a <= b on _Float16 values to vcomish xmm1, xmm0 with SETA or SETAE, the operands swapped as COMISS’s page explains, and uses VUCOMISH for ==; Clang 23 uses VUCOMISH for all three, as it does for floats. The intrinsics part ways with their single-precision ones, which GCC compiles to VCOMISS as that page shows: for _mm_comi_round_sh, _mm_comilt_sh and _mm_comieq_sh both compilers emit VCMPSH into K0 with the matching predicate, {sae} where asked, and read the bit with KMOVB or KMOVW. Without AVX512-FP16, as with -march=znver5, both widen the halves with VCVTPH2PS and compare singles, which gives the same order since every half is exactly a single: GCC with VCOMISS for <, Clang with VUCOMISS.

AVX10.2 adds VCOMXSH, the same opcode with an F3 prefix, which also sets OF and SF so that the signed conditions such as JL and JLE test less than directly. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCOMISH.

Forms

Every encoding of VCOMISH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCOMISH xmm, xmm, {sae}` VCOMISH_XMMf16_XMMf16_AVX512	`EVEX.LIG.NP.MAP5.W0 2F /r`	AVX10.1 or AVX512_FP16
`VCOMISH xmm, m16` VCOMISH_XMMf16_MEMf16_AVX512	`EVEX.LIG.NP.MAP5.W0 2F /r`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, {sae}`	`xmm, m16`
Sapphire Rapids	4 / 1p0	10 / 1p0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low halves of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from half 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = comi(xmm1.f16[0], src2.f16[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# a QNaN raises IE too
# {sae}: no exception flags

Not run on a processor: none of these processors has AVX512-FP16.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCOMISH xmm, xmm/m16, {sae}`
`xmm`	explicit	read
`xmm/m16`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

In our builds#