VCOMISS instruction (AVX, AVX10.1)

VCOMISS is COMISS in VEX and EVEX encodings: it compares the low singles of a register and a register or four bytes of memory, sets ZF, PF and CF, and raises the invalid-operation exception for a NaN of either kind. COMISS’s page explains the flags, the swapped operands for “less than”, and why GCC picks it for < where Clang picks VUCOMISS. Since it writes no register, the newer encodings add no third operand and zero nothing. The VEX form needs AVX; the EVEX form needs AVX512F or AVX10.1 and brings XMM16 to XMM31 and {sae}, which suppresses every floating-point exception. Neither takes a write mask.

Intel’s table ignores VEX.L but asks for L = 0, warning that L = 1 may behave differently across generations. AMD’s VEX encoding names a source register in VEX.vvvv, while its own exception list raises #UD unless the field is 1111b, as Intel’s does.

Recorded on Zen 5

vcomiss xmm4, xmm4, with the quiet NaN 7FC12345h, gave unordered (ZF, PF and CF set) and set IE, MXCSR going from 3FC0H to 3FC1H.
{evex} vcomiss xmm17, xmm30, {sae} compared two quiet NaNs under 1E40H, whose clear IM and DM bits unmask the invalid-operation and denormal exceptions: the result was unordered, with no fault and no flag.
{evex} vcomiss xmm5, dword ptr [mem], a quiet NaN against a signaling one under FFC0H, set IE.

In compiled code

In our builds at -O2 with -march=x86-64-v3 or -v4, the scalar compares of COMISS’s page take the VEX encoding and change nothing else: GCC 14 compiles a < b on floats to vcomiss xmm1, xmm0 and SETA. AVX-512’s _mm_comi_round_ss(a, b, pred, sae) shows the two compilers apart: GCC emits VCOMISS for a signaling predicate such as _CMP_LT_OS and VUCOMISS for a quiet one such as _CMP_LT_OQ, with {sae} for _MM_FROUND_NO_EXC, while Clang 23 emits VCMPSS into K0 with that predicate, and {sae} where asked, followed by KMOVW, and leaves EFLAGS alone.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows two macro-ops, on pipes FP2/FP3 and FP4/FP5, two per cycle, and no latency, since no register is written. VCOMISD is the double form.

Forms

Every encoding of VCOMISS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCOMISS xmm, m32` VCOMISS_XMMd_MEMd	`VEX.LIG.NP.0F.WIG 2F /r`	AVX
`VCOMISS xmm, xmm` VCOMISS_XMMd_XMMd	`VEX.LIG.NP.0F.WIG 2F /r`	AVX
`VCOMISS xmm, xmm, {sae}` VCOMISS_XMMf32_XMMf32_AVX512	`EVEX.LIG.NP.0F.W0 2F /r`	AVX10.1 or AVX512F
`VCOMISS xmm, m32` VCOMISS_XMMf32_MEMf32_AVX512	`EVEX.LIG.NP.0F.W0 2F /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, m32`	`xmm, xmm` `xmm, xmm, {sae}`
Sandy Bridge	8 / 1p01	2 / 1p01
Haswell, Broadwell	8 / 1p1	3 / 1p1
Skylake, Skylake-SP, Ice Lake	7 / 1p0	2 / 1p0
Alder Lake, Sapphire Rapids	8 / 1p0	3 / 1p0
Lunar Lake	9 / 2V0 V1	3 / 1.5V0 V1
Piledriver	6 / 1.5EX0 FPFMA FPU0	1 / 1EX0 FPFMA FPU0
Zen, Zen 2	10 / 1FPU0 FPU1 FPU2	3 / 1FPU0 FPU1 FPU2
Zen 3, Zen 4	11 / 1FP0 FP1	4 / 1FP0 FP1
Jaguar	8 / 1ALU0 FPA FPU0	3 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low singles of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from single 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = comi(xmm1.f32[0], src2.f32[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# a QNaN raises IE too
# {sae}: no exception flags

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCOMISS xmm, xmm/m32` `VCOMISS xmm, xmm/m32, {sae}`
`xmm`	explicit	read
`xmm/m32`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
VEX forms
0	0	M	0	M	M
EVEX forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-3
EVEX forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCOMISS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_comieq_ss` `int _mm_comieq_ss(__m128 __a, __m128 __b)`	`VCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_comige_ss` `int _mm_comige_ss(__m128 __a, __m128 __b)`	`VCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_comigt_ss` `int _mm_comigt_ss(__m128 __a, __m128 __b)`	`VCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_comile_ss` `int _mm_comile_ss(__m128 __a, __m128 __b)`	`VCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_comilt_ss` `int _mm_comilt_ss(__m128 __a, __m128 __b)`	`VCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_comineq_ss` `int _mm_comineq_ss(__m128 __a, __m128 __b)`	`VCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#