VCOMPRESSPD

VCOMPRESSPD packs the doubles that a mask selects at the low end of its destination, in their original order: 2, 4 or 8 at a time, so the mask of a full ZMM register fits in a byte. It is VPCOMPRESSQ under a floating-point name, and VPCOMPRESSD’s page explains left-packing and the register and memory destinations; VCOMPRESSPS packs singles. The bits are moved as they are. It came with AVX512F.

Recorded on Zen 5#

• To memory. vcompresspd zmmword ptr [mem]{k2}, zmm0, with C9h in the low byte of K2, wrote elements 0, 3, 6 and 7 to the first 32 bytes and left the other 32 as they were.
• Nothing selected. The XMM memory form with the low two bits of K6 clear wrote nothing.
• Merging. vcompresspd zmm7{k6}, zmm12, with A4h in the low byte of K6, packed elements 2, 5 and 7 into elements 0 to 2 and kept the other five of ZMM7; the XMM form with both bits of K7 set copied the source and cleared the register above bit 127.
• Zeroing. vcompresspd ymm14{k7}{z}, ymm8, with bits 0 and 1 of the four set, kept two elements and cleared the rest.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 keep the loop if (pd[i] > 0) po[n++] = pd[i]; over doubles scalar. VCOMPRESSPD comes from the intrinsics: _mm512_maskz_compress_pd is the zeroing register form, after a KMOVB of the mask in GCC and a KMOVD in Clang.

AMD’s Zen 5 latency spreadsheet gives the register forms two macro-ops on pipes FP1 and FP2, with 2, 4 and 5 cycles for XMM, YMM and ZMM, and lists the memory form as microcoded.

In the optimization guide

What the optimization guide says about VCOMPRESSPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: VPCOMPRESSD and the other compress instructions are microcoded when they write to memory: compressing into a register and then storing it is faster.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 64):
    if k1[i]:
        mem.q[j] = zmm2.q[i]
        j += 1
# the memory above element j is not written

j = 0
for i in range(VL // 64):
    if k1[i]:
        zmm1.q[j] = zmm2.q[i]
        j += 1
if zeroing:
    for i in range(j, VL // 64):
        zmm1.q[i] = 0
# else: the elements from j up keep their values
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCOMPRESSPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW

All 686 AVX10.1 instructions