VCOMPRESSPS

VCOMPRESSPS packs the singles that a mask selects at the low end of its destination, in their original order, 4, 8 or 16 at a time. It is VPCOMPRESSD under a floating-point name, and that page explains left-packing and the two destinations: a register, whose remaining elements are kept or zeroed, and memory, where only as many singles as the mask selects are written, one after another. The bits are moved, not converted, so MXCSR never changes. VCOMPRESSPD packs doubles and VEXPANDPS does the reverse. It came with AVX512F.

Recorded on Zen 5#

• To memory. vcompressps zmmword ptr [mem]{k2}, zmm24, with F2C9h in the low 16 bits of K2, wrote elements 0, 3, 6, 7, 9 and 12 to 15, nine singles, to the first 36 bytes and left the other 28 as they were.
• Merging. vcompressps zmm14{k1}, zmm8 put its five selected elements at the bottom of ZMM14 and kept the other eleven of ZMM14, not zeroed.
• Zeroing. vcompressps ymm1{k4}{z}, ymm2 packed five elements and cleared the remaining three and the register above bit 255.
• One element. The XMM memory form with only bit 2 of the four set wrote element 2 to the first four bytes and nothing else.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 do not vectorize if (f[i] > 0) fo[n++] = f[i]; over floats: both keep it scalar, with or without -march=znver5. VCOMPRESSPS comes only from the intrinsics, _mm512_mask_compressstoreu_ps for the memory form, the mask moved in with KMOVW in GCC and KMOVD in Clang.

AMD’s Zen 5 latency spreadsheet gives the register forms two macro-ops on pipes FP1 and FP2, with 2, 4 and 5 cycles for XMM, YMM and ZMM, and lists the memory form as microcoded.

In the optimization guide

What the optimization guide says about VCOMPRESSPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: VPCOMPRESSD and VPEXPANDD replace shuffle tables, but compressing straight to memory is microcode on Zen 4 and Zen 5.

Zen 4

• Vectors and floating point: VPCOMPRESSD and the other compress instructions are microcoded when they write to memory: compressing into a register and then storing it is faster.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 32):
    if k1[i]:
        mem.d[j] = zmm2.d[i]
        j += 1
# the memory above element j is not written

j = 0
for i in range(VL // 32):
    if k1[i]:
        zmm1.d[j] = zmm2.d[i]
        j += 1
if zeroing:
    for i in range(j, VL // 32):
        zmm1.d[i] = 0
# else: the elements from j up keep their values
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCOMPRESSPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W

All 686 AVX10.1 instructions