VCOMXSD instruction (AVX10.2)

VCOMXSD compares the low doubles of a register and a register or eight bytes of memory and sets OF, SF, ZF, PF and CF so that each relation, less than included, is one condition code, as VCOMXSS’s page lists. Like VCOMISD, it raises the invalid-operation exception for any NaN, quiet ones included; VUCOMXSD does so only for signaling NaNs. It belongs to AVX10.2 and exists only in EVEX form: opcode 2Fh in map 0F with W1, as VCOMISD, but with an F2 prefix where VCOMISD has 66.

Four flag patterns

The AVX10.2 specification (revision 7.0) sets five flags for each of the four outcomes and clears AF:

Outcome	OF	SF	ZF	PF	CF
greater	0	0	0	0	0
less	1	0	0	0	1
equal	1	1	1	0	0
unordered	1	1	0	1	1

An unordered result clears ZF, where VCOMISD sets ZF, PF and CF together, so JE alone tests equality. SF equals OF except for “less”, which makes JL and JLE exact, and CF is set for “less” and “unordered”, which leaves JA and JAE false for a NaN. The specification’s opcode line says LLIG, the vector length ignored, but its exception list raises #UD when EVEX.L’L is not 00b.

In our builds

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles the intrinsic _mm_comieq_sd to VCOMXSD and SETE, and _mm_comineq_sd to VCOMXSD and SETNE; for -march=x86-64-v4 the first takes VCOMISD, SETNP, SETE and an AND. _mm_comilt_sd keeps VCOMISD with the operands swapped and SETA in both. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Every encoding of VCOMXSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCOMXSD xmm, xmm, {sae}` VCOMXSD_XMMf64_XMMf64_AVX512	`EVEX.LIG.F2.0F.W1 2F /r`	AVX10.2
`VCOMXSD xmm, m64` VCOMXSD_XMMf64_MEMf64_AVX512	`EVEX.LIG.F2.0F.W1 2F /r`	AVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low doubles of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from double 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = comx(xmm1.f64[0], src2.f64[0])  # 0 >, 1 <, 2 =, 3 unordered
of = x != 0
sf = x in (2, 3)
zf = x == 2
pf = x == 3
cf = x in (1, 3)
af = 0
# a QNaN raises IE too
# {sae}: no exception flags

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCOMXSD xmm, xmm/m64, {sae}`
`xmm`	explicit	read
`xmm/m64`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512_COM_EF_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Four flag patterns#

In our builds#