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Instruction

VCOMXSS

Compares the low singles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

COMISS and UCOMISS, like their VEX and EVEX forms VCOMISS and VUCOMISS, set ZF, PF and CF as if for an unsigned compare, and an unordered result (a NaN input) sets all three. Testing for “equal” therefore needs a second check of the parity flag, and “less than” works only with the operands swapped.

VCOMXSS sets OF, SF, ZF, PF and CF so that every relation is one condition code, false when the result is unordered:

RelationCondition
greaterA
greater or equalAE
equalE
less or equalLE
lessL
orderedNP

The inverse conditions (NA, NAE, NE, NLE, NL, P) are true for unordered inputs. VCOMXSS signals an invalid operation for any NaN input; VUCOMXSS does so only for signaling NaNs. The double-precision (VCOMXSD) and half-precision (VCOMXSH) versions work the same way.

Forms

Every encoding of VCOMXSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCOMXSS xmm, xmm, {sae} VCOMXSS_XMMf32_XMMf32_AVX512EVEX.LIG.F3.0F.W0 2F /rAVX10.2
VCOMXSS xmm, m32 VCOMXSS_XMMf32_MEMf32_AVX512EVEX.LIG.F3.0F.W0 2F /rAVX10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_COM_EF_SCALAR

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.