VCOMXSS instruction (AVX10.2)

COMISS and UCOMISS, like their VEX and EVEX forms VCOMISS and VUCOMISS, set ZF, PF and CF as if for an unsigned compare, and an unordered result (a NaN input) sets all three. Testing for “equal” therefore needs a second check of the parity flag, and “less than” works only with the operands swapped.

VCOMXSS sets OF, SF, ZF, PF and CF so that every relation is one condition code, false when the result is unordered:

Relation	Condition
greater	A
greater or equal	AE
equal	E
less or equal	LE
less	L
ordered	NP

The inverse conditions (NA, NAE, NE, NLE, NL, P) are true for unordered inputs. VCOMXSS signals an invalid operation for any NaN input; VUCOMXSS does so only for signaling NaNs. The double-precision (VCOMXSD) and half-precision (VCOMXSH) versions work the same way.

Forms

Every encoding of VCOMXSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCOMXSS xmm, xmm, {sae}` VCOMXSS_XMMf32_XMMf32_AVX512	`EVEX.LIG.F3.0F.W0 2F /r`	AVX10.2
`VCOMXSS xmm, m32` VCOMXSS_XMMf32_MEMf32_AVX512	`EVEX.LIG.F3.0F.W0 2F /r`	AVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low singles of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from single 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = comx(xmm1.f32[0], src2.f32[0])  # 0 >, 1 <, 2 =, 3 unordered
of = x != 0
sf = x in (2, 3)
zf = x == 2
pf = x == 3
cf = x in (1, 3)
af = 0
# a QNaN raises IE too
# {sae}: no exception flags

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCOMXSS xmm, xmm/m32, {sae}`
`xmm`	explicit	read
`xmm/m32`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512_COM_EF_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions