x86-64.net

Instruction

VCVT2PH2BF8S

Converts two vectors of half-precision values into one vector of E5M2 FP8 values, saturating values too large for FP8 to its largest normal.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVT2PH2BF8S that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVT2PH2BF8S xmm {k}{z}, xmm, xmm VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512EVEX.128.F2.MAP5.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVT2PH2BF8S xmm {k}{z}, xmm, m128/m16bcst VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512EVEX.128.F2.MAP5.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVT2PH2BF8S ymm {k}{z}, ymm, ymm VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512EVEX.256.F2.MAP5.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVT2PH2BF8S ymm {k}{z}, ymm, m256/m16bcst VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512EVEX.256.F2.MAP5.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVT2PH2BF8S zmm {k}{z}, zmm, zmm VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512EVEX.512.F2.MAP5.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVT2PH2BF8S zmm {k}{z}, zmm, m512/m16bcst VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512EVEX.512.F2.MAP5.W0 74 /rAVX10.2 or AVX10_V1_AUX

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVT2PH2BF8S, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvts_2ph_bf8 __m128i _mm_cvts_2ph_bf8(__m128h __A, __m128h __B)

VCVT2PH2BF8S xmm, xmm, xmm EVEX.128 -mavx10.2

_mm_mask_cvts_2ph_bf8 __m128i _mm_mask_cvts_2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B)

VCVT2PH2BF8S xmm {k}, xmm, xmm EVEX.128 -mavx10.2

_mm_maskz_cvts_2ph_bf8 __m128i _mm_maskz_cvts_2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B)

VCVT2PH2BF8S xmm {k}{z}, xmm, xmm EVEX.128 -mavx10.2

_mm256_cvts_2ph_bf8 __m256i _mm256_cvts_2ph_bf8(__m256h __A, __m256h __B)

VCVT2PH2BF8S ymm, ymm, ymm EVEX.256 -mavx10.2

_mm256_mask_cvts_2ph_bf8 __m256i _mm256_mask_cvts_2ph_bf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B)

VCVT2PH2BF8S ymm {k}, ymm, ymm EVEX.256 -mavx10.2

_mm256_maskz_cvts_2ph_bf8 __m256i _mm256_maskz_cvts_2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B)

VCVT2PH2BF8S ymm {k}{z}, ymm, ymm EVEX.256 -mavx10.2

_mm512_cvts_2ph_bf8 __m512i _mm512_cvts_2ph_bf8(__m512h __A, __m512h __B)

VCVT2PH2BF8S zmm, zmm, zmm EVEX.512 -mavx10.2

_mm512_mask_cvts_2ph_bf8 __m512i _mm512_mask_cvts_2ph_bf8(__m512i __W, __mmask64 __U, __m512h __A, __m512h __B)

VCVT2PH2BF8S zmm {k}, zmm, zmm EVEX.512 -mavx10.2

_mm512_maskz_cvts_2ph_bf8 __m512i _mm512_maskz_cvts_2ph_bf8(__mmask64 __U, __m512h __A, __m512h __B)

VCVT2PH2BF8S zmm {k}{z}, zmm, zmm EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP8_CONVERT_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_FP8_CONVERT_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_FP8_CONVERT_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.