VCVT2PH2BF8S

VCVT2PH2BF8S narrows the half-precision values of two registers into one register of 8-bit floats in the E5M2 format (a sign, 5 exponent bits and 2 fraction bits), saturating values too large for it. The third operand, which may be memory or a broadcast half, fills the low half of the destination and the second operand the high half, so two zmm registers of 32 halves give one zmm register of 64 bytes. It belongs to AVX10.2, opcode 74h with the F2 prefix in EVEX map 5, and takes a write mask of bytes. VCVT2PH2BF8 is the form without saturation, in map 0F38, and VCVTPH2BF8S narrows one source into half a register. VADDPH covers the half-precision format.

A rounded top byte#

E5M2 has FP16’s exponent width and bias, 15, so it is a half with its low 8 fraction bits cut away. The conversion in the AVX10.2 specification works that way: it adds a rounding bias to the half, round to nearest even whatever MXCSR says, and keeps the upper byte. Denormal halves convert like the others, as DAZ and FTZ are not obeyed, and MXCSR is neither read nor written: no flag, no exception. A NaN keeps its top byte with the quiet bit set.

Saturation#

The largest E5M2 value is 57,344 (1.75 × 2^15). A half that would round above it gives 57,344 with its sign instead of infinity, which VCVT2PH2BF8 returns. The specification’s text and its pseudocode saturate an infinite input too, but its Table 3.6 lists infinity at the input of the saturating forms as giving infinity.

In our builds#

GCC 14 has no AVX10.2. Clang 23 with -mavx10.2 compiles _mm512_cvts_2ph_bf8(a, b) to vcvt2ph2bf8s zmm0, zmm0, zmm1, so its first argument, a, becomes the high half; the masked form takes its 64-bit mask from a general register with KMOVQ, and _mm256_ and _mm_ forms exist. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:
        if i < VL // 16:
            x = src3.f16[i]
        else:
            x = zmm2.f16[i - VL // 16]
        zmm1.bf8[i] = to_bf8s(x)
    elif zeroing:
        zmm1.bf8[i] = 0
    # else: zmm1.bf8[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# BF8: to nearest even, denormals kept, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVT2PH2BF8S, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions