VCVT2PH2HF8

VCVT2PH2HF8 converts the half-precision values of two registers to E4M3 and packs them into one: the third operand, which may be memory or a broadcast half, fills the low half of the destination and the second operand the high half, so two zmm registers of 32 halves give 64 bytes. Each byte is what VCVTPH2HF8 gives for the same half, rounded to nearest even: halves above 464, infinities and NaNs become the NaN, 7Fh or FFh by sign, halves below 2^-6 become E4M3 denormals, and those of 2^-10 or less a zero. MXCSR is neither read nor written and nothing is flagged. It belongs to AVX10.2, opcode 18h with the F2 prefix in EVEX map 5, and its write mask has one bit per byte, up to 64. VCVT2PH2HF8S saturates at 448 instead.

An example#

With 1.0 in the low word of the third operand and the half nearest 0.1 (2E66h) in the low word of the second, a 128-bit conversion puts 38h in byte 0 and 1Dh, which is 0.1015625, in byte 8: the second operand’s eight halves go to bytes 8 to 15. A half of 1000 in either source gives 7Fh, and -1000 gives FFh.

In our builds#

GCC 14 rejects -mavx10.2. Clang 23 compiles _mm512_cvt2ph_hf8(a, b) to vcvt2ph2hf8 zmm0, zmm0, zmm1, so a fills the high half. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:
        if i < VL // 16:
            x = src3.f16[i]
        else:
            x = zmm2.f16[i - VL // 16]
        zmm1.hf8[i] = to_hf8(x)
    elif zeroing:
        zmm1.hf8[i] = 0
    # else: zmm1.hf8[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# HF8: to nearest even, denormals kept, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVT2PH2HF8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions