VCVT2PH2HF8S

VCVT2PH2HF8S is VCVT2PH2HF8 with saturation: it converts the halves of two registers to E4M3 into one register, the third operand’s halves to the low half of the destination and the second operand’s to the high half, and gives 448, the largest E4M3 value, with the half’s sign wherever the plain form would give the NaN for a value too large: 7Eh for a half above 464 and FEh below -464. A NaN still gives 7Fh or FFh. Rounding is to nearest even whatever MXCSR says, denormal results are kept, and nothing is flagged. It is opcode 1Bh with the F2 prefix in EVEX map 5, takes a broadcast half and a write mask of up to 64 bits, and VCVTPH2HF8S is the one-source form.

Infinity#

For an infinite half the AVX10.2 specification differs with itself, as VCVTPH2HF8S’s page explains: its description and helper function give 448 of the same sign, which the Operation block here follows, and its Table 3.6 gives the NaN.

In our builds#

GCC 14 rejects -mavx10.2. Clang 23 compiles _mm512_cvts_2ph_hf8(a, b) to vcvt2ph2hf8s zmm0, zmm0, zmm1, so a fills the high half; _mm256_ and _mm_ forms exist. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:
        if i < VL // 16:
            x = src3.f16[i]
        else:
            x = zmm2.f16[i - VL // 16]
        zmm1.hf8[i] = to_hf8s(x)
    elif zeroing:
        zmm1.hf8[i] = 0
    # else: zmm1.hf8[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# HF8: to nearest even, denormals kept, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVT2PH2HF8S, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions