VCVT2PS2PHX

VCVT2PS2PHX narrows two registers of singles into one register of half precision values: the third operand, a register, memory or one single broadcast from memory, fills the low half of the destination, and the second operand, always a register, the high half. Two xmm, ymm or zmm sources of 4, 8 or 16 singles give 8, 16 or 32 halves in a register of the same size, under a write mask of one bit per half. It is the two-source form of VCVTPS2PHX, as VCVTNE2PS2BF16 is for bfloat16, with the same order of halves. AVX10.2 added it: opcode 67h with the 66 prefix in map 0F38, W0, and CPUID reports it with AVX10.2 or with the narrower AVX10_V1_AUX bit, leaf 24H, subleaf 1, ECX bit 2.

Rounding and MXCSR#

Each single is rounded to a half by MXCSR.RC, or by {er}, which only the 512-bit register form takes: revision 7 of AVX10.2 dropped the rounding control of the ymm form. DAZ applies to the singles, but a result too small for a normal half stays a half denormal whatever FTZ says, as with VCVTPS2PHX. AVX10.2’s description says that the instruction sets the flags in MXCSR as if every exception were masked and raises no floating-point exception; its exception table gives class E2, which revision 6 changed from E4NF, and that class includes #XM for an unmasked exception.

In our builds#

GCC 14 has no -mavx10.2. In Clang 23 with -mavx10.2, _mm512_cvtx2ps_ph(a, b) becomes vcvt2ps2phx zmm0, zmm0, zmm1 with a in zmm0 and b in zmm1, so the first argument ends up in the high half. A loop h[i] = f[i] from a float array to a _Float16 array, at -O2 with -march=x86-64-v4 -mavx10.2, does not use it: Clang narrows each ymm register with VCVTPS2PHX and stores every xmm result on its own. This site’s recorded cases include none of VCVT2PS2PHX.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        if i < VL // 32:
            x = src3.f32[i]
        else:
            x = zmm2.f32[i - VL // 32]
        zmm1.f16[i] = to_f16(x)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVT2PS2PHX, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions