Instruction
VCVT2PS2PHX
Converts two vectors of single-precision values into one vector of half-precision values, rounding as MXCSR or the instruction selects.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCVT2PS2PHX xmm {k}{z}, xmm, xmm
VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512 | EVEX.128.66.0F38.W0 67 /r | AVX10.2 or AVX10_V1_AUX |
VCVT2PS2PHX xmm {k}{z}, xmm, m128/m32bcst
VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512 | EVEX.128.66.0F38.W0 67 /r | AVX10.2 or AVX10_V1_AUX |
VCVT2PS2PHX ymm {k}{z}, ymm, ymm
VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512 | EVEX.256.66.0F38.W0 67 /r | AVX10.2 or AVX10_V1_AUX |
VCVT2PS2PHX ymm {k}{z}, ymm, m256/m32bcst
VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512 | EVEX.256.66.0F38.W0 67 /r | AVX10.2 or AVX10_V1_AUX |
VCVT2PS2PHX zmm {k}{z}, zmm, zmm, {er}
VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512 | EVEX.512.66.0F38.W0 67 /r | AVX10.2 or AVX10_V1_AUX |
VCVT2PS2PHX zmm {k}{z}, zmm, m512/m32bcst
VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512 | EVEX.512.66.0F38.W0 67 /r | AVX10.2 or AVX10_V1_AUX |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VCVT2PS2PHX, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvtx2ps_ph
__m128h _mm_cvtx2ps_ph(__m128 __A, __m128 __B) |
|
_mm_mask_cvtx2ps_ph
__m128h _mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) |
|
_mm_maskz_cvtx2ps_ph
__m128h _mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) |
|
_mm256_cvtx2ps_ph
__m256h _mm256_cvtx2ps_ph(__m256 __A, __m256 __B) |
|
_mm256_mask_cvtx2ps_ph
__m256h _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) |
|
_mm256_maskz_cvtx2ps_ph
__m256h _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) |
|
_mm512_cvtx2ps_ph
__m512h _mm512_cvtx2ps_ph(__m512 __A, __m512 __B) |
|
_mm512_cvtx_round2ps_ph
__m512h _mm512_cvtx_round2ps_ph(__m512 A, __m512 B, const int R) |
|
_mm512_mask_cvtx2ps_ph
__m512h _mm512_mask_cvtx2ps_ph(__m512h __W, __mmask32 __U, __m512 __A, __m512 __B) |
|
_mm512_mask_cvtx_round2ps_ph
__m512h _mm512_mask_cvtx_round2ps_ph(__m512h W, __mmask32 U, __m512 A, __m512 B, const int R) |
|
_mm512_maskz_cvtx2ps_ph
__m512h _mm512_maskz_cvtx2ps_ph(__mmask32 __U, __m512 __A, __m512 __B) |
|
_mm512_maskz_cvtx_round2ps_ph
__m512h _mm512_maskz_cvtx_round2ps_ph(__mmask32 U, __m512 A, __m512 B, const int R) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_CONVERT_128 | AVX10.2 or AVX10_V1_AUX | Nova Lake, Diamond Rapids |
AVX512_FP16_CONVERT_256 | AVX10.2 or AVX10_V1_AUX | Nova Lake, Diamond Rapids |
AVX512_FP16_CONVERT_512 | AVX10.2 or AVX10_V1_AUX | Nova Lake, Diamond Rapids |
More AVX10.2 instructions
- VADDBF16
- VCMPBF16
- VCOMISBF16
- VCOMXSD
- VCOMXSH
- VCOMXSS
- VCVT2PH2BF8
- VCVT2PH2BF8S
- VCVT2PH2HF8
- VCVT2PH2HF8S
- VCVTBF162IBS
- VCVTBF162IUBS
- VCVTBIASPH2BF8
- VCVTBIASPH2BF8S
- VCVTBIASPH2HF8
- VCVTBIASPH2HF8S
- VCVTHF82PH
- VCVTPH2BF8
- VCVTPH2BF8S
- VCVTPH2HF8
- VCVTPH2HF8S
- VCVTPH2IBS
- VCVTPH2IUBS
- VCVTPS2IBS
- VCVTPS2IUBS
- VCVTTBF162IBS
- VCVTTBF162IUBS
- VCVTTPD2DQS
- VCVTTPD2QQS
- VCVTTPD2UDQS
- VCVTTPD2UQQS
- VCVTTPH2IBS
- VCVTTPH2IUBS
- VCVTTPS2DQS
- VCVTTPS2IBS
- VCVTTPS2IUBS
- VCVTTPS2QQS
- VCVTTPS2UDQS
- VCVTTPS2UQQS
- VCVTTSD2SIS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.