VCVTBF82BF4S instruction (AVX10_V2_AUX)

VCVTBF82BF4S converts E5M2 bytes to the 4-bit E2M1 format, which the mnemonics call BF4: a sign, 2 exponent bits with a bias of 1 and 1 fraction bit. Its magnitudes are 0, 0.5, 1, 1.5, 2, 3, 4 and 6, with no infinity and no NaN. Two results share each byte, element i in bits 4i+3:4i, so element 0 is the low nibble, and the 16, 32 or 64 bytes of an xmm, ymm or zmm source give 8, 16 or 32 bytes. The destination is the ModRM r/m operand: an xmm or ymm register, cleared above the result, or memory, where only the result’s bytes are written. There is no write mask. It belongs to AVX10_V2_AUX of the ACE specification, opcode 3Dh with the F3 prefix in EVEX map 5, W1; with W0 it is VCVTHF82BF4S, from E4M3.

Rounding and saturation

Values round to nearest even, whatever MXCSR says, and nothing is flagged. With one fraction bit, ties are common: 5 gives 4, 2.5 gives 2, 1.25 gives 1, 0.75 gives 1 and 0.25 gives 0, while 1.75 gives 2. Anything above 6, from 7 up, an infinity and a NaN all give 6 with their sign (7h or Fh). E5M2’s denormals, below 2^-14, lie far under 0.25 and round to zeros, as ACE notes; DAZ does not apply. VCVTBF42HF8 widens E2M1 back, to E4M3.

ACE 1.16 corrected the operand order: the destination is the r/m operand and the source the reg operand, as for VCVTPS2PH, so the result can go straight to memory.

In our builds

GCC 14 and Clang 23 have no option for AVX10_V2_AUX: Clang 23’s assembler and GNU as 2.44 reject the mnemonic, and ACE’s intrinsic _mm512_cvtf8_bf4s is missing from Clang 23’s headers. This site’s recorded cases include none of VCVTBF82BF4S.

Forms

Every encoding of VCVTBF82BF4S that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCVTBF82BF4S xmm, xmm` VCVTBF82BF4S_XMMbf4_XMMbf8_AVX512	`EVEX.128.F3.MAP5.W1 3D /r`	AVX10_V2_AUX + AVX10
`VCVTBF82BF4S m64, xmm` VCVTBF82BF4S_MEMbf4_XMMbf8_AVX512	`EVEX.128.F3.MAP5.W1 3D /r`	AVX10_V2_AUX + AVX10
`VCVTBF82BF4S xmm, ymm` VCVTBF82BF4S_XMMbf4_YMMbf8_AVX512	`EVEX.256.F3.MAP5.W1 3D /r`	AVX10_V2_AUX + AVX10
`VCVTBF82BF4S m128, ymm` VCVTBF82BF4S_MEMbf4_YMMbf8_AVX512	`EVEX.256.F3.MAP5.W1 3D /r`	AVX10_V2_AUX + AVX10
`VCVTBF82BF4S ymm, zmm` VCVTBF82BF4S_YMMbf4_ZMMbf8_AVX512	`EVEX.512.F3.MAP5.W1 3D /r`	AVX10_V2_AUX + AVX10
`VCVTBF82BF4S m256, zmm` VCVTBF82BF4S_MEMbf4_ZMMbf8_AVX512	`EVEX.512.F3.MAP5.W1 3D /r`	AVX10_V2_AUX + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Narrow: each byte becomes a 4-bit element, in the same order, at the low end of the result; the rest of the register is zeroed.Register forms

Shown for the xmm form; the ymm and zmm forms work the same on 32 and 64 bytes.

Result 4-bit elements 31 to 0: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, a15, a14, a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.

Narrow: each byte becomes a 4-bit element, in the same order, at the low end of the result.Memory forms

A memory destination receives the 4-bit elements alone. Shown for the xmm form; the ymm and zmm forms work the same on 32 and 64 bytes.

Result 4-bit elements 15 to 0: a15, a14, a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    ymm1.bf4[i] = to_bf4s(zmm2.bf8[i])
for i in range(VL // 8, 32):
    ymm1.bf4[i] = 0
# BF4: to nearest even, denormals kept, no flags; MXCSR unused
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Not run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.

Memory forms

for i in range(VL // 8):
    mem.bf4[i] = to_bf4s(zmm2.bf8[i])
# BF4: to nearest even, denormals kept, no flags; MXCSR unused

Not run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCVTBF82BF4S xmm/m64, xmm` `VCVTBF82BF4S xmm/m128, ymm` `VCVTBF82BF4S ymm/m256, zmm`
`xmm/m64, xmm/m128, ymm/m256`	explicit	write
`xmm, ymm, zmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E4NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX10_V2_AUX_128` AVX10_V2_AUX	AVX10_V2_AUX + AVX10 `CPUID.(EAX=24H,ECX=1):ECX[3]` AVX10_V2_AUX `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
`AVX10_V2_AUX_256` AVX10_V2_AUX	Same as `AVX10_V2_AUX_128`	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
`AVX10_V2_AUX_512` AVX10_V2_AUX	Same as `AVX10_V2_AUX_128`	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

VCVTBF82BF4S

Rounding and saturation

In our builds

Forms

Data flow

Operation

Operands

Flags

Exceptions

CPUID and processors

More AVX10_V2_AUX instructions

Sources

Rounding and saturation#

In our builds#

Forms

Data flow

Operation

Operands

Flags

Exceptions

CPUID and processors

More AVX10_V2_AUX instructions

Sources

Rounding and saturation

In our builds