VCVTBF82BF6S instruction (AVX10_V2_AUX)

VCVTBF82BF6S converts E5M2 bytes to the 6-bit E3M2 format, which the mnemonics call BF6: a sign, 3 exponent bits with a bias of 3 and 2 fraction bits, with no infinity and no NaN. The 6-bit results are packed with no gaps, element i in bits 6i+5:6i, so four of them fill three bytes: the 16, 32 or 64 bytes of an xmm, ymm or zmm register become the low 96, 192 or 384 bits of a register of the same size, and the bits above are cleared. Both operands are registers, and there is no write mask. It belongs to AVX10_V2_AUX of the ACE specification, opcode 3Eh with the F3 prefix in EVEX map 5, W1. VCVTHF82HF6S converts E4M3 to the other 6-bit format, and VCVTBF62HF8 widens E3M2 to E4M3.

Same fraction, shorter exponent

E3M2 keeps E5M2’s two fraction bits, so every value in its normal range, 0.25 to 28, converts exactly; only the exponent field shrinks. Larger values, from 32 up, an infinity and a NaN all give 28 with their sign (1Fh or 3Fh). Below 0.25 the result is an E3M2 denormal in steps of 0.0625, rounded to nearest even: 0.046875 gives 0.0625, while 0.03125, a tie, gives zero. E5M2’s own denormals lie far below and give zeros. MXCSR is neither read nor written, and nothing is flagged.

In our builds

GCC 14 and Clang 23 have no option for AVX10_V2_AUX: Clang 23’s assembler and GNU as 2.44 reject the mnemonic, and ACE’s intrinsic _mm512_cvtf8_bf6s is missing from Clang 23’s headers. Zen 5, whose CPUID reports no AVX10, raised #UD in all three recorded cases.

Forms

Every encoding of VCVTBF82BF6S that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCVTBF82BF6S xmm, xmm` VCVTBF82BF6S_XMMbf6_XMMbf8_AVX512	`EVEX.128.F3.MAP5.W1 3E /r`	AVX10_V2_AUX + AVX10
`VCVTBF82BF6S ymm, ymm` VCVTBF82BF6S_YMMbf6_YMMbf8_AVX512	`EVEX.256.F3.MAP5.W1 3E /r`	AVX10_V2_AUX + AVX10
`VCVTBF82BF6S zmm, zmm` VCVTBF82BF6S_ZMMbf6_ZMMbf8_AVX512	`EVEX.512.F3.MAP5.W1 3E /r`	AVX10_V2_AUX + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Narrow to 6 bits: each byte becomes a 6-bit element, converted, the elements packed with no gaps from bit 0 up, element i in bits 6i+5:6i; above the last of them, the register is zeroed.

Shown: bytes 7 to 0 of xmm2 and the elements they make, in bits 47:0 of xmm1, each over its bits. Every byte works alike: 16, 32 and 64 in the xmm, ymm and zmm forms, whose elements fill bits 95:0, 191:0 and 383:0.

Result 6-bit element i, in bits 6i+5:6i, is byte i of xmm2, converted. Result 6-bit elements 7 to 0: a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)                    # CPUID: no AVX10
if not cpuid_leaf(0x24, 1)[2] >> 3 & 1:
    fault(UD)                    # CPUID: no AVX10_V2_AUX
for i in range(VL // 8):         # byte i to bits 6i+5:6i
    zmm1.bf6[i] = to_bf6s(zmm2.bf8[i])
for i in range(3 * VL // 128, VL // 32):
    zmm1.d[i] = 0                # bits 3VL/4 to VL-1
# E5M2 to E3M2, to nearest even; what is
# too large, an infinity or a NaN gives
# 28 of its sign; no flags, MXCSR unused
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no AVX10.2, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCVTBF82BF6S xmm, xmm` `VCVTBF82BF6S ymm, ymm` `VCVTBF82BF6S zmm, zmm`
`xmm, ymm, zmm`	explicit	write
`xmm, ymm, zmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX10_V2_AUX_128` AVX10_V2_AUX	AVX10_V2_AUX + AVX10 `CPUID.(EAX=24H,ECX=1):ECX[3]` AVX10_V2_AUX `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
`AVX10_V2_AUX_256` AVX10_V2_AUX	Same as `AVX10_V2_AUX_128`	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
`AVX10_V2_AUX_512` AVX10_V2_AUX	Same as `AVX10_V2_AUX_128`	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

VCVTBF82BF6S

Same fraction, shorter exponent

In our builds

Forms

Data flow

Operation

Operands

Flags

Exceptions

CPUID and processors

More AVX10_V2_AUX instructions

Sources

Same fraction, shorter exponent#

In our builds#

Forms

Data flow

Operation

Operands

Flags

Exceptions

CPUID and processors

More AVX10_V2_AUX instructions

Sources

Same fraction, shorter exponent

In our builds