x86-64.net

Instruction

VCVTBIASPH2BF8

Converts packed half-precision values to E5M2 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTBIASPH2BF8 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTBIASPH2BF8 xmm {k}{z}, xmm, xmm VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512EVEX.128.NP.0F38.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVTBIASPH2BF8 xmm {k}{z}, xmm, m128/m16bcst VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128EVEX.128.NP.0F38.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVTBIASPH2BF8 xmm {k}{z}, ymm, ymm VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512EVEX.256.NP.0F38.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVTBIASPH2BF8 xmm {k}{z}, ymm, m256/m16bcst VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256EVEX.256.NP.0F38.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVTBIASPH2BF8 ymm {k}{z}, zmm, zmm VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512EVEX.512.NP.0F38.W0 74 /rAVX10.2 or AVX10_V1_AUX
VCVTBIASPH2BF8 ymm {k}{z}, zmm, m512/m16bcst VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512EVEX.512.NP.0F38.W0 74 /rAVX10.2 or AVX10_V1_AUX

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTBIASPH2BF8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtbiasph_bf8 __m128i _mm_cvtbiasph_bf8(__m128i __A, __m128h __B)

VCVTBIASPH2BF8 xmm, xmm, xmm EVEX.128 -mavx10.2

_mm_mask_cvtbiasph_bf8 __m128i _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B)

VCVTBIASPH2BF8 xmm {k}, xmm, xmm EVEX.128 -mavx10.2

_mm_maskz_cvtbiasph_bf8 __m128i _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B)

VCVTBIASPH2BF8 xmm {k}{z}, xmm, xmm EVEX.128 -mavx10.2

_mm256_cvtbiasph_bf8 __m128i _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B)

VCVTBIASPH2BF8 xmm, ymm, ymm EVEX.256 -mavx10.2

_mm256_mask_cvtbiasph_bf8 __m128i _mm256_mask_cvtbiasph_bf8(__m128i __W, __mmask16 __U, __m256i __A, __m256h __B)

VCVTBIASPH2BF8 xmm {k}, ymm, ymm EVEX.256 -mavx10.2

_mm256_maskz_cvtbiasph_bf8 __m128i _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B)

VCVTBIASPH2BF8 xmm {k}{z}, ymm, ymm EVEX.256 -mavx10.2

_mm512_cvtbiasph_bf8 __m256i _mm512_cvtbiasph_bf8(__m512i __A, __m512h __B)

VCVTBIASPH2BF8 ymm, zmm, zmm EVEX.512 -mavx10.2

_mm512_mask_cvtbiasph_bf8 __m256i _mm512_mask_cvtbiasph_bf8(__m256i __W, __mmask32 __U, __m512i __A, __m512h __B)

VCVTBIASPH2BF8 ymm {k}, zmm, zmm EVEX.512 -mavx10.2

_mm512_maskz_cvtbiasph_bf8 __m256i _mm512_maskz_cvtbiasph_bf8(__mmask32 __U, __m512i __A, __m512h __B)

VCVTBIASPH2BF8 ymm {k}{z}, zmm, zmm EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP8_CONVERT_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_FP8_CONVERT_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_FP8_CONVERT_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.