VCVTBIASPH2BF8S

VCVTBIASPH2BF8S is VCVTBIASPH2BF8 with saturation: it adds the bias byte to each half’s bits and keeps the upper byte, and where the result would be infinity, from a half too large or from the bias’s carry, it gives 57,344 (1.75 × 2^15), the largest E5M2 value, with the half’s sign. FP16’s largest value, 65,504, therefore gives 57,344 whatever the bias. It takes the halves from the third operand, which may be memory or a broadcast half, and the biases from the low bytes of the second operand’s words; it is opcode 74h without a prefix in EVEX map 5, where the plain form sits in map 0F38. NaNs come out quiet, MXCSR is unused and nothing is flagged.

Two disagreements#

An infinite half gives 57,344 in AVX10.2’s description of these instructions, in its helper function and in ACE, and the Operation block here follows them; AVX10.2’s Table 3.6 lists infinity for infinity at the input of the saturating E5M2 forms. For a denormal half, below 2^-14, the documents place the bias differently or drop it, as VCVTBIASPH2BF8’s page sets out, and the block leaves the result UNDEFINED where they differ.

Recorded and built#

Zen 5, whose CPUID reports no AVX10, raised #UD for all seven recorded forms. GCC 14 rejects -mavx10.2. Clang 23 compiles _mm512_cvts_biasph_bf8(b, a), the biases first, to vcvtbiasph2bf8s ymm0, zmm0, zmm1.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)                    # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)                    # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 16):
    if k1[i]:
        x = src3.f16[i]          # FP16 element i
        b = zmm2.b[2 * i]        # its bias: word i's low byte
        a = x & 0x7FFF           # |x|, as bits
        r = (x + b) >> 8         # E5M2 is FP16's high byte: the
                                 # bias below its last place, the
                                 # sum cut there
        if a > 0x7C00:
            r = x >> 8 | 2       # a NaN, quieted
        elif (r & 0x7F) == 0x7C: # infinity, or past the largest:
            r -= 1               # the largest, 57344, of its sign
        elif 0 < a < 0x400:      # a denormal; r is AVX10.2's
                                 # reading (5.1, 9.3.2)
            n = to_bf8(x)        # AVX10.2's 3.2.2: to nearest
                                 # even, no bias
            k = lzcnt(a, 10) + 1
            u = ((a << k) + b) >> (8 + k)
                                 # ACE (16.2): a normalized
                                 # first, the bias k bits lower
            if r != n or (r & 0x7F) != u:
                r = UNDEFINED    # the readings differ
        ymm1.bf8[i] = r
    elif zeroing:
        ymm1.bf8[i] = 0
    # else: ymm1.bf8[i] keeps its value
for i in range(VL // 16, 16):
    ymm1.b[i] = 0
# m16bcst: src3.f16[i] is the m16 for every i
# no flags; MXCSR unused, denormals kept
# documents: AVX10.2 rev. 7, ACE 1.16.2
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTBIASPH2BF8S, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions