VCVTBIASPH2HF8

VCVTBIASPH2HF8 converts half-precision values to E4M3 with a rounding bias, as VCVTBIASPH2BF8 does for E5M2: the halves come from the third operand, which may be memory or a broadcast half, and the bias of half i is the low byte of word i of the second operand. A zmm register of each gives 32 bytes in a ymm register, the bits above cleared. It is opcode 18h without a prefix in EVEX map 5, with a write mask of one bit per result byte. VCVTPH2HF8 is the conversion rounded to nearest even, and covers the format.

Seven bits, not eight#

E4M3 keeps 3 of the half’s 10 fraction bits, so a normal result drops 7 bits, and the bias is shifted right by one before it is added below the result’s last place. Its lowest bit is lost: biases 2k and 2k + 1 act alike, 0 and 1 truncate, 254 and 255 round away from zero, and a uniformly random byte rounds away with probability d/128 for a dropped value d. The sum then loses its 7 low bits and its exponent is rebased from 15 to 7.

E4M3 has no infinity, so a result of 480 or more becomes the NaN, 7Fh or FFh by sign, as do infinities and NaNs. The bias alone can get there: 479.75 (5F7Fh) gives 448 with a bias of 0 or 1 and the NaN with any larger one. VCVTBIASPH2HF8S gives 448 instead. MXCSR is neither read nor written, and nothing is flagged.

Small results#

Below 2^-6 the results are E4M3 denormals, and there the documents differ. AVX10.2’s helper function puts all 8 bits of the bias below the denormal’s last place; ACE’s helper and AVX10.2’s own description add the halved bias at the same bits as for a normal result, further below that place, so it carries less often, and for the smallest halves never. The Operation block computes both and leaves the result UNDEFINED where they differ.

Recorded and built#

Zen 5, whose CPUID reports no AVX10, raised #UD for all seven recorded forms. GCC 14 rejects -mavx10.2. Clang 23 compiles _mm512_cvtbiasph_hf8(b, a), the biases first, to vcvtbiasph2hf8 ymm0, zmm0, zmm1.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)                    # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)                    # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 16):
    if k1[i]:
        x = src3.f16[i]          # FP16 element i
        b = zmm2.b[2 * i]        # its bias: word i's low byte
        s = x >> 8 & 0x80        # the sign, in place
        a = x & 0x7FFF           # |x|, as bits
        if a >= 0x7C00:          # infinity or NaN: the NaN
            r = s | 0x7F
        elif a >= 0x2400:        # 2^-6 and up: a normal
            t = (a + (b >> 1)) >> 7
                                 # 7 bits of bias below E4M3's
                                 # last place, the sum cut there
            r = s | min(t - 0x40, 0x7F)
                                 # the exponent rebiased, 15 to
                                 # 7; 480 and up: the NaN
        else:                    # below 2^-6, an E4M3 denormal
            n = max(a >> 10, 1)  # a's exponent field (1 for a
                                 # denormal), its significand m
            m = a - ((n - 1) << 10)
            q = 16 - n           # E4M3's last place: bit q of m
            u = (m + (b >> 1)) >> q
                                 # ACE (16.2) and AVX10.2's text
                                 # (9.3.2): as for a normal
            r = s | u
            c = b << (8 - n)     # AVX10.2's helper (5.1): all 8
                                 # bits of bias below bit q
            if (m + c) >> q != u:
                r = UNDEFINED    # the readings differ
        ymm1.hf8[i] = r
    elif zeroing:
        ymm1.hf8[i] = 0
    # else: ymm1.hf8[i] keeps its value
for i in range(VL // 16, 16):
    ymm1.b[i] = 0
# m16bcst: src3.f16[i] is the m16 for every i
# no flags; MXCSR unused, denormals kept
# documents: AVX10.2 rev. 7, ACE 1.16.2
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTBIASPH2HF8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions