VCVTBIASPS2BF8S

VCVTBIASPS2BF8S is VCVTBIASPS2BF8 with saturation. Each single, from the third operand, gets the low 21 bits of the matching bias doubleword of the second operand added below E5M2’s last place and is then cut to E5M2, so that a bias of 0 truncates and random biases round stochastically; the bytes go to the low end of an xmm register under a write mask of one bit per byte. Where the sum would reach infinity, and for an infinite single, the result is the largest finite value, 57,344 (7Bh), with the single’s sign. A NaN still gives a quiet NaN. The encoding is opcode 3Bh with no prefix in EVEX map 5, W0, in AVX10_V2_AUX of the ACE specification.

Why the bias makes it matter#

Without saturation, the bias alone can push a finite single over the top: any value from 57,344 up to 65,536 becomes infinity once the bias carries into the exponent, which with random biases happens in proportion to how far the value lies past 57,344. With this form those values stay at 57,344. ACE’s table and its pseudocode agree here, as they do for VCVTPS2BF8S, which saturates after rounding to nearest even. MXCSR is neither read nor written, a denormal single counts as a zero, and nothing is flagged.

In our builds#

GCC 14 and Clang 23 have no option for AVX10_V2_AUX: Clang 23’s assembler and GNU as 2.44 reject the mnemonic, and ACE’s intrinsic _mm512_cvtbiaspss_bf8 is missing from Clang 23’s headers. Zen 5, whose CPUID reports no AVX10, raised #UD in all seven recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)                    # CPUID: no AVX10
if not cpuid_leaf(0x24, 1)[2] >> 3 & 1:
    fault(UD)                    # no AVX10_V2_AUX
for i in range(VL // 32):
    if k1[i]:
        x = src3.f32[i]          # single i
        c = zmm2.d[i] & 0x1FFFFF # its bias: doubleword i's
                                 # bits 20:0
        s = x >> 24 & 0x80       # the sign, in place
        a = x & 0x7FFFFFFF       # |x|, as bits
        t = a + c                # the bias below E5M2's last
                                 # place at a's exponent
        e = t >> 23              # the sum's exponent
        if a > 0x7F800000:       # a NaN: quieted, the top bit
                                 # of its payload kept
            r = s | 0x7E | x >> 21 & 1
        elif a < 0x800000:       # zero or denormal: a zero
            r = s
        elif e > 112:            # 2^-14 and up: a normal
            r = (t >> 21) - 0x1C0
                                 # cut, the exponent rebiased
                                 # (127 to 15)
            r = s | min(r, 0x7B) # infinity, and past the
                                 # largest: 57344
        else:                    # below: an E5M2 denormal
            m = t & 0x7FFFFF | 0x800000
            r = s | m >> (134 - e)  # cut at 2^-16
        xmm1.bf8[i] = r
    elif zeroing:
        xmm1.bf8[i] = 0
    # else: xmm1.bf8[i] keeps its value
for i in range(VL // 32, 16):
    xmm1.b[i] = 0
# m32bcst: src3.f32[i] is the m32 for every i
# no flags; MXCSR unused, a denormal single a zero
# document: ACE 1.16.2
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10_V2_AUX instructions

• VCVTBF42HF8
• VCVTBF62HF8
• VCVTBF82BF4S
• VCVTBF82BF6S
• VCVTBF82PS
• VCVTBIASPS2BF8
• VCVTBIASPS2HF8
• VCVTBIASPS2HF8S
• VCVTHF62HF8
• VCVTHF82BF4S
• VCVTHF82HF6S
• VCVTHF82PS
• VCVTPS2BF8
• VCVTPS2BF8S
• VCVTPS2HF8
• VCVTPS2HF8S
• VCVTROPS2HF8
• VCVTROPS2HF8S
• VPMOVSSDB
• VUNPACKB