VCVTDQ2PD

VCVTDQ2PD converts signed doublewords to doubles, always exactly: four from an xmm register or 16 bytes into a ymm register with VEX, eight from a ymm register into a zmm one with EVEX. CVTDQ2PD explains why no rounding or flag is possible and how compilers widen an array in halves, and VCVTDQ2PS is the conversion to singles, which does round. Being exact, the EVEX form takes neither a rounding mode nor {sae}; what it adds is masking per double and a broadcast doubleword.

Exact where singles are not#

The cases recorded on Zen 5 show integers that a single cannot hold: 16,777,217, 16,777,219 and 2,147,483,647 came back as themselves, as did -2,147,483,647 and -2^31 in the EVEX form. MXCSR came back unchanged in every case, whatever its rounding field said.

Masks per double#

Each mask bit selects one result double. With E1H in the low byte of K5, vcvtdq2pd zmm14{k5}, ymm8 wrote doubles 0, 5, 6 and 7 and kept the other four; the 256-bit form with a memory source and the same mask wrote only double 0, since it uses only the mask’s low four bits.

Unsigned integers#

For unsigned elements the signed conversion is wrong from 2^31 up, and our builds at -O2 handle that in three ways. For -march=x86-64-v3, GCC 14 converts as signed, compares the results with zero and adds 2^32 to the negative ones through an AND mask, and Clang 23 zero-extends with VPMOVZXDQ and places the integers in the significand of 2^52 before subtracting it. For x86-64-v4, GCC keeps VCVTDQ2PD on zmm registers but compares into a mask register with VCMPPD and adds 2^32 with a masked VADDPD, while Clang switches to AVX-512’s VCVTUDQ2PD.

For signed integers, GCC widens a loaded vector in two halves around VEXTRACTI128 (VEXTRACTI32X8 for x86-64-v4), and Clang converts straight from memory, to ymm registers for x86-64-v3 and x86-64-v4 and to zmm for znver5.

In the optimization guide

What the optimization guide says about VCVTDQ2PD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.f64[i] = to_f64(src2.sd[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTDQ2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD

All 253 AVX instructions

More AVX10.1 instructions

• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ

All 686 AVX10.1 instructions