VCVTDQ2PH

VCVTDQ2PH converts signed doublewords to half precision, the vector form of C’s conversion from int to _Float16. The result is half as wide as the source: 16 doublewords of a ZMM register become 16 halves in a YMM register, 8 from a YMM register fill an XMM register, and 4 from an XMM register fill its low 64 bits, with everything above cleared. The opcode is that of CVTDQ2PS, 5Bh without a prefix, in EVEX map 5; VCVTUDQ2PH converts unsigned doublewords, and VADDPH covers AVX512-FP16 and the format.

Most integers do not fit#

A half has 11 significant bits and a largest finite value of 65504, so only integers up to 2048 in magnitude are all exact (Intel’s optimization manual, Section 18.5.2), and most of the 32-bit range lies beyond the format. The conversion rounds by MXCSR.RC, or by an {er} mode on the 512-bit register form, and a result past 65504 becomes an infinity: Intel’s entry lists overflow and precision, where the conversion to singles, which never overflows, lists only precision. In round to nearest, 65519 still becomes 65504 and 65520 is the first to become infinity, since it lies halfway to 65536 and 65504 has an odd significand; rounding toward zero gives 65504 for every larger value.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, h[i] = a[i] from an int array to a _Float16 array becomes VCVTDQ2PH with the source in memory in GCC 14 and Clang 23: GCC converts two ZMM loads and joins the YMM halves with VINSERTI64X4 for one ZMM store, Clang converts YMM loads to XMM results. A single int is converted with VCVTSI2SH. Without AVX512-FP16, at -march=x86-64-v3, Clang uses VCVTDQ2PS and VCVTPS2PH, which gives the same halves because every integer up to 2^24 is exact as a single and the larger ones overflow a half either way; GCC converts each element to a double and calls the library’s __truncdfhf2. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTDQ2PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        ymm1.f16[i] = to_f16(src2.sd[i])
    elif zeroing:
        ymm1.f16[i] = 0
    # else: ymm1.f16[i] keeps its value
for i in range(VL // 32, 8):
    ymm1.w[i] = 0
# m32bcst: src2.d[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTDQ2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD

All 686 AVX10.1 instructions