VCVTDQ2PS

VCVTDQ2PS is CVTDQ2PS in VEX and EVEX encodings. The CVTDQ2PS page explains which integers convert exactly (all up to 2^24 in magnitude), how the others round and how compilers handle unsigned integers; the VEX forms add 256 bits and clear the bits above the result, and the EVEX forms add 512 bits, masking, a broadcast doubleword from memory and, for a register source, a rounding mode given in the instruction.

Rounding on Zen 5#

The cases recorded on Zen 5 show both ways of choosing the rounding. With MXCSR set to round up, the VEX form converted 16,777,217 to 16,777,218, 16,777,219 to 16,777,220 and 2,147,483,647 to 2^31, and set the precision flag. The EVEX form with {ru-sae} rounded 16,777,217 up to 16,777,218 too, although MXCSR asked to round toward zero, and with the precision exception unmasked it neither faulted nor set a flag.

In compiled code#

GCC 14 and Clang 23 at -O2 convert (float)a[i] over an int array with VCVTDQ2PS on ymm registers for -march=x86-64-v3, on zmm for znver5, and for -march=x86-64-v4 on zmm in GCC and ymm in Clang. The unsigned conversion shows what each level brings:

• for x86-64-v3, GCC splits each element into its high and low 16 bits, converts both with VCVTDQ2PS and joins them with one VFMADD132PS, high times 65,536 plus low, which rounds once;
• Clang, for the same target, converts without VCVTDQ2PS, blending the halves into the significands of two constants with VPBLENDW and removing them with VSUBPS and VADDPS;
• for x86-64-v4, both use the AVX-512 instruction VCVTUDQ2PS.

AMD’s Zen 5 guide lists VCVTDQ2PS as one macro-op with a latency of 3 cycles at every width. VCVTDQ2PD converts to doubles, always exactly.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.f32[i] = to_f32(src2.sd[i])
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTDQ2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS

All 253 AVX instructions

More AVX10.1 instructions

• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH

All 686 AVX10.1 instructions