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Instruction

VCVTHF62HF8

Converts packed 6-bit E2M3 floating-point values to E4M3 FP8, which is exact.

Extensions
Forms
3 (3 EVEX)
Data
Intel XED v2026.08.23

VCVTHF62HF8 widens 6-bit E2M3 values to E4M3 bytes, exactly, as VCVTBF62HF8 does for E3M2: element i, from bits 6i+5:6i of the source register, goes to byte i of a register of the same size under a write mask of one bit per byte, and the source’s top quarter is not read. There is no memory operand. It belongs to AVX10_V2_AUX of the ACE specification, opcode 37h with the 66 prefix in EVEX map 5, W0. It undoes VCVTHF82HF6S.

The same fraction

E2M3 has the three fraction bits of E4M3 and a bias of 1 instead of 7, so a normal value only gets 6 added to its exponent: 1Fh (7.5) gives 4Fh, and 08h (1.0) gives 38h. Its denormals, 0.125 to 0.875 in steps of 0.125, are normal numbers in E4M3: 01h gives 20h (0.125) and 07h gives 36h (0.875). The sign moves from bit 5 to bit 7, so 20h, a negative zero, gives 80h. E2M3 has no infinity or NaN, MXCSR is neither read nor written, and nothing is flagged.

In our builds

GCC 14 and Clang 23 have no option for AVX10_V2_AUX: Clang 23’s assembler and GNU as 2.44 reject the mnemonic, and ACE’s list of intrinsics names none for it; _mm512_cvtf6_hf8 is the E3M2 form’s, and Clang 23’s headers lack both. Zen 5, whose CPUID reports no AVX10, raised #UD in all six recorded cases.

Forms

Every encoding of VCVTHF62HF8 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTHF62HF8 xmm {k}{z}, xmm VCVTHF62HF8_XMMhf8_MASKmskw_XMMhf6_AVX512EVEX.128.66.MAP5.W0 37 /rAVX10_V2_AUX + AVX10
VCVTHF62HF8 ymm {k}{z}, ymm VCVTHF62HF8_YMMhf8_MASKmskw_YMMhf6_AVX512EVEX.256.66.MAP5.W0 37 /rAVX10_V2_AUX + AVX10
VCVTHF62HF8 zmm {k}{z}, zmm VCVTHF62HF8_ZMMhf8_MASKmskw_ZMMhf6_AVX512EVEX.512.66.MAP5.W0 37 /rAVX10_V2_AUX + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen from 6 bits: each 6-bit element of the source, packed with no gaps, element i in bits 6i+5:6i, becomes a byte, converted, in the same order; the source's bits above them are not read.
VCVTHF62HF8: 6-bit elements packedResult byte i is 6-bit element i of xmm2, from its bits 6i+5:6i, converted. Result bytes 7 to 0: a7, unchanged (bit 6 of k1 is 0), a5, a4, a3, a2, a1, a0.5:011:617:1223:1829:2435:3041:3647:42bits…01234567xmm2a11111110k1…a0a1a2a3a4a5a7xmm1

Shown: the elements 7 to 0 of xmm2, in its bits 47:0, each under its bits, and bytes 7 to 0 of xmm1. Every element works alike: 16, 32 and 64 in the xmm, ymm and zmm forms, from bits 95:0, 191:0 and 383:0. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result byte i is 6-bit element i of xmm2, from its bits 6i+5:6i, converted. Result bytes 7 to 0: a7, unchanged (bit 6 of k1 is 0), a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)                    # CPUID: no AVX10
if not cpuid_leaf(0x24, 1)[2] >> 3 & 1:
    fault(UD)                    # CPUID: no AVX10_V2_AUX
for i in range(VL // 8):         # bits 6i+5:6i to byte i
    x = to_hf8(zmm2.hf6[i])      # exact
    if k1[i]:                    # 1 without a write mask
        zmm1.hf8[i] = x
    elif zeroing:
        zmm1.hf8[i] = 0
    # else: zmm1.hf8[i] keeps its value
# no flags, MXCSR unused
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases. Its cases ran where CPUID reported no AVX10.2, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VCVTHF62HF8 xmm {k}{z}, xmm VCVTHF62HF8 ymm {k}{z}, ymm VCVTHF62HF8 zmm {k}{z}, zmm
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E7NM

Attributes

What else XED records about the forms. How to read.

All forms
write masking

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX10_V2_AUX_128

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_256
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_512
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More AVX10_V2_AUX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.