x86-64.net

Instruction

VCVTHF82BF4S

Converts packed E4M3 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTHF82BF4S that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTHF82BF4S xmm, xmm VCVTHF82BF4S_XMMbf4_XMMhf8_AVX512EVEX.128.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S m64, xmm VCVTHF82BF4S_MEMbf4_XMMhf8_AVX512EVEX.128.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S xmm, ymm VCVTHF82BF4S_XMMbf4_YMMhf8_AVX512EVEX.256.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S m128, ymm VCVTHF82BF4S_MEMbf4_YMMhf8_AVX512EVEX.256.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S ymm, zmm VCVTHF82BF4S_YMMbf4_ZMMhf8_AVX512EVEX.512.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S m256, zmm VCVTHF82BF4S_MEMbf4_ZMMhf8_AVX512EVEX.512.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX10_V2_AUX_128

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_256

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_512

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.

More AVX10_V2_AUX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.