x86-64.net

Instruction

VCVTHF82BF4S

Converts packed E4M3 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

VCVTHF82BF4S converts E4M3 bytes to the 4-bit E2M1 format and packs two to a byte, element i in bits 4i+3:4i, as VCVTBF82BF4S does from E5M2: 16, 32 or 64 bytes give 8, 16 or 32, written to the r/m operand, a register cleared above the result or memory, with no write mask. It belongs to AVX10_V2_AUX of the ACE specification, opcode 3Dh with the F3 prefix in EVEX map 5, W0.

From three fraction bits to one

E4M3 has two more fraction bits than E2M1, so most values round, to nearest even with MXCSR unused and nothing flagged: 5.0 (4Ah) gives 4, 5.5 (4Bh) gives 6, 3.5 gives 4 and 0.75 gives 1. Values above 6, up to 448, saturate to 6 with their sign, and so does the NaN, 7Fh or FFh. E4M3’s denormals, below 2^-6, and everything up to 0.25 give zeros.

Converting singles in two steps rounds twice. VCVTROPS2HF8, which rounds to odd, makes the pair round as once: a single a little above 5 should give 6, and does through VCVTROPS2HF8’s 5.5, while VCVTPS2HF8’s 5.0 is a tie that gives 4.

In our builds

GCC 14 and Clang 23 have no option for AVX10_V2_AUX: Clang 23’s assembler and GNU as 2.44 reject the mnemonic. ACE’s list of intrinsics names _mm512_cvtf8_bf4s only for the E5M2 form, and Clang 23’s headers have neither. This site’s recorded cases include none of VCVTHF82BF4S.

Forms

Every encoding of VCVTHF82BF4S that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTHF82BF4S xmm, xmm VCVTHF82BF4S_XMMbf4_XMMhf8_AVX512EVEX.128.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S m64, xmm VCVTHF82BF4S_MEMbf4_XMMhf8_AVX512EVEX.128.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S xmm, ymm VCVTHF82BF4S_XMMbf4_YMMhf8_AVX512EVEX.256.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S m128, ymm VCVTHF82BF4S_MEMbf4_YMMhf8_AVX512EVEX.256.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S ymm, zmm VCVTHF82BF4S_YMMbf4_ZMMhf8_AVX512EVEX.512.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10
VCVTHF82BF4S m256, zmm VCVTHF82BF4S_MEMbf4_ZMMhf8_AVX512EVEX.512.F3.MAP5.W0 3D /rAVX10_V2_AUX + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Narrow: each byte becomes a 4-bit element, in the same order, at the low end of the result; the rest of the register is zeroed.Register forms
VCVTHF82BF4S: each element narrowedResult 4-bit elements 31 to 0: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, a15, a14, a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.0123456789101112131415xmm2aa0a1a2a3a4a5a6a7a8a9a10a11a12a13a14a150xmm1

Shown for the xmm form; the ymm and zmm forms work the same on 32 and 64 bytes.

Result 4-bit elements 31 to 0: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, a15, a14, a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.

Narrow: each byte becomes a 4-bit element, in the same order, at the low end of the result.Memory forms
VCVTHF82BF4S: each element narrowedResult 4-bit elements 15 to 0: a15, a14, a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.0123456789101112131415xmm2aa0a1a2a3a4a5a6a7a8a9a10a11a12a13a14a15m64

A memory destination receives the 4-bit elements alone. Shown for the xmm form; the ymm and zmm forms work the same on 32 and 64 bytes.

Result 4-bit elements 15 to 0: a15, a14, a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

Register forms
for i in range(VL // 8):
    ymm1.bf4[i] = to_bf4s(zmm2.hf8[i])
for i in range(VL // 8, 32):
    ymm1.bf4[i] = 0
# BF4: to nearest even, denormals kept, no flags; MXCSR unused
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Not run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.

Memory forms
for i in range(VL // 8):
    mem.bf4[i] = to_bf4s(zmm2.hf8[i])
# BF4: to nearest even, denormals kept, no flags; MXCSR unused

Not run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VCVTHF82BF4S xmm/m64, xmm VCVTHF82BF4S xmm/m128, ymm VCVTHF82BF4S ymm/m256, zmm
xmm/m64, xmm/m128, ymm/m256explicitwrite
xmm, ymm, zmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E4NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX10_V2_AUX_128

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_256
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_512
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More AVX10_V2_AUX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.