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Instruction

VCVTHF82HF6S

Converts packed E4M3 FP8 values to the 6-bit E2M3 format, rounding to nearest even and saturating out-of-range values.

Extensions
Forms
3 (3 EVEX)
Data
Intel XED v2026.08.23

VCVTHF82HF6S converts E4M3 bytes to the 6-bit E2M3 format, which the mnemonics call HF6: a sign, 2 exponent bits with a bias of 1 and 3 fraction bits, with no infinity and no NaN. It packs the results as VCVTBF82BF6S does, element i in bits 6i+5:6i of a register of the source’s size, the top quarter cleared, with no write mask and no memory operand. It belongs to AVX10_V2_AUX of the ACE specification, opcode 3Ch with the F3 prefix in EVEX map 5, W0; the E5M2 form is 3Eh, not the same opcode with W1 as for the FP4 pair, 3Dh.

A narrow range

E2M3 keeps E4M3’s three fraction bits, so values from 1 to its largest, 7.5, convert exactly: 5.5 (4Bh) gives 1Bh. Everything larger, from 8 up to 448, and the NaN give 7.5 with their sign (1Fh or 3Fh). Below 1 the results are E2M3 denormals in steps of 0.125, rounded to nearest even: 0.1875 gives 0.25, and 0.0625, a tie, gives zero; E4M3’s denormals, below 2^-6, give zeros. MXCSR is neither read nor written, and nothing is flagged. VCVTHF62HF8 converts back, exactly, so E4M3 values from 1 to 7.5 survive the round trip.

In our builds

GCC 14 and Clang 23 have no option for AVX10_V2_AUX: Clang 23’s assembler and GNU as 2.44 reject the mnemonic. ACE’s list of intrinsics names _mm512_cvtf8_bf6s only for the E5M2 form, and Clang 23’s headers have neither. Zen 5, whose CPUID reports no AVX10, raised #UD in all three recorded cases.

Forms

Every encoding of VCVTHF82HF6S that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTHF82HF6S xmm, xmm VCVTHF82HF6S_XMMhf6_XMMhf8_AVX512EVEX.128.F3.MAP5.W0 3C /rAVX10_V2_AUX + AVX10
VCVTHF82HF6S ymm, ymm VCVTHF82HF6S_YMMhf6_YMMhf8_AVX512EVEX.256.F3.MAP5.W0 3C /rAVX10_V2_AUX + AVX10
VCVTHF82HF6S zmm, zmm VCVTHF82HF6S_ZMMhf6_ZMMhf8_AVX512EVEX.512.F3.MAP5.W0 3C /rAVX10_V2_AUX + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Narrow to 6 bits: each byte becomes a 6-bit element, converted, the elements packed with no gaps from bit 0 up, element i in bits 6i+5:6i; above the last of them, the register is zeroed.
VCVTHF82HF6S: 6-bit elements packedResult 6-bit element i, in bits 6i+5:6i, is byte i of xmm2, converted. Result 6-bit elements 7 to 0: a7, a6, a5, a4, a3, a2, a1, a0.…01234567xmm2a…a0a1a2a3a4a5a6a7xmm15:011:617:1223:1829:2435:3041:3647:42bits

Shown: bytes 7 to 0 of xmm2 and the elements they make, in bits 47:0 of xmm1, each over its bits. Every byte works alike: 16, 32 and 64 in the xmm, ymm and zmm forms, whose elements fill bits 95:0, 191:0 and 383:0.

Result 6-bit element i, in bits 6i+5:6i, is byte i of xmm2, converted. Result 6-bit elements 7 to 0: a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)                    # CPUID: no AVX10
if not cpuid_leaf(0x24, 1)[2] >> 3 & 1:
    fault(UD)                    # CPUID: no AVX10_V2_AUX
for i in range(VL // 8):         # byte i to bits 6i+5:6i
    zmm1.hf6[i] = to_hf6s(zmm2.hf8[i])
for i in range(3 * VL // 128, VL // 32):
    zmm1.d[i] = 0                # bits 3VL/4 to VL-1
# E4M3 to E2M3, to nearest even; what is
# too large, or a NaN, gives 7.5 of its
# sign; no flags, MXCSR unused
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no AVX10.2, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VCVTHF82HF6S xmm, xmm VCVTHF82HF6S ymm, ymm VCVTHF82HF6S zmm, zmm
xmm, ymm, zmmexplicitwrite
xmm, ymm, zmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E7NM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX10_V2_AUX_128

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_256
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_512
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More AVX10_V2_AUX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.