VCVTHF82PH

VCVTHF82PH widens E4M3 values to half precision. Every E4M3 number, denormals included, is a normal half or a zero, since FP16’s exponents reach down to 2^-14 and its 10 fraction bits hold E4M3’s 3, so the result is exact: no rounding, no flag, no exception, MXCSR unused. The bytes come from the low half of the source: 32 bytes from a ymm register or memory give 32 halves in a zmm register, and the 128-bit form reads 8 bytes, an m64. There is no broadcast form. It belongs to AVX10.2, opcode 1Eh with the F2 prefix in EVEX map 5, with a write mask of one bit per half. VCVTPH2HF8 converts the other way, rounding.

Some values#

E4M3’s largest number, 448 (7Eh), becomes 5F00h, and its smallest denormal, 2^-9 (01h), becomes 1800h, a normal half. The NaN, 7Fh, becomes 7F80h, a quiet half NaN, and FFh becomes FF80h. A conversion to E4M3 and back with this instruction therefore rounds a half to E4M3’s precision, except that values too large, and infinities, come back as NaN.

No E5M2 counterpart#

There is no instruction for E5M2, since an E5M2 byte is the upper byte of the half it stands for: Clang 23 compiles _mm512_cvtbf8_ph to VPMOVZXBW and vpsllw zmm0, zmm0, 8, while _mm512_cvthf8_ph gives vcvthf82ph zmm0, ymm0. GCC 14 rejects -mavx10.2. ACE adds conversions of both 8-bit formats to singles, VCVTHF82PS and VCVTBF82PS.

Its exception class#

Revision 7.0 of the AVX10.2 specification moved the instruction from exception class E2 to E4, because it raises no SIMD floating-point exception and leaves MXCSR alone. The two classes differ in E2’s #XM, which this exact conversion never raises, and in E4’s #UD for an EVEX.b that the instruction gives no meaning, which matters here, as there is no broadcast. The ACE specification, version 1.16.2, still lists the instruction under E2 in its table of classes, and its revision 1.14 calls that a correction. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.f16[i] = to_f16(src2.hf8[i])
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# HF8: exact, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTHF82PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions