x86-64.net

Instruction

VCVTHF82PH

Converts packed E4M3 FP8 values to half precision, which is exact.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTHF82PH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTHF82PH xmm {k}{z}, xmm VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512EVEX.128.F2.MAP5.W0 1E /rAVX10.2 or AVX10_V1_AUX
VCVTHF82PH xmm {k}{z}, m64 VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512EVEX.128.F2.MAP5.W0 1E /rAVX10.2 or AVX10_V1_AUX
VCVTHF82PH ymm {k}{z}, xmm VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512EVEX.256.F2.MAP5.W0 1E /rAVX10.2 or AVX10_V1_AUX
VCVTHF82PH ymm {k}{z}, m128 VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512EVEX.256.F2.MAP5.W0 1E /rAVX10.2 or AVX10_V1_AUX
VCVTHF82PH zmm {k}{z}, ymm VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512EVEX.512.F2.MAP5.W0 1E /rAVX10.2 or AVX10_V1_AUX
VCVTHF82PH zmm {k}{z}, m256 VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512EVEX.512.F2.MAP5.W0 1E /rAVX10.2 or AVX10_V1_AUX

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTHF82PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvthf8_ph __m128h _mm_cvthf8_ph(__m128i __A)

VCVTHF82PH xmm, xmm EVEX.128 -mavx10.2

_mm_mask_cvthf8_ph __m128h _mm_mask_cvthf8_ph(__m128h __W, __mmask8 __U, __m128i __A)

VCVTHF82PH xmm {k}, xmm EVEX.128 -mavx10.2

_mm_maskz_cvthf8_ph __m128h _mm_maskz_cvthf8_ph(__mmask8 __U, __m128i __A)

VCVTHF82PH xmm {k}{z}, xmm EVEX.128 -mavx10.2

_mm256_cvthf8_ph __m256h _mm256_cvthf8_ph(__m128i __A)

VCVTHF82PH ymm, xmm EVEX.256 -mavx10.2

_mm256_mask_cvthf8_ph __m256h _mm256_mask_cvthf8_ph(__m256h __W, __mmask16 __U, __m128i __A)

VCVTHF82PH ymm {k}, xmm EVEX.256 -mavx10.2

_mm256_maskz_cvthf8_ph __m256h _mm256_maskz_cvthf8_ph(__mmask16 __U, __m128i __A)

VCVTHF82PH ymm {k}{z}, xmm EVEX.256 -mavx10.2

_mm512_cvthf8_ph __m512h _mm512_cvthf8_ph(__m256i __A)

VCVTHF82PH zmm, ymm EVEX.512 -mavx10.2

_mm512_mask_cvthf8_ph __m512h _mm512_mask_cvthf8_ph(__m512h __W, __mmask32 __U, __m256i __A)

VCVTHF82PH zmm {k}, ymm EVEX.512 -mavx10.2

_mm512_maskz_cvthf8_ph __m512h _mm512_maskz_cvthf8_ph(__mmask32 __U, __m256i __A)

VCVTHF82PH zmm {k}{z}, ymm EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP8_CONVERT_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_FP8_CONVERT_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_FP8_CONVERT_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.