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Instruction

VCVTHF82PS

Converts packed E4M3 FP8 values to single precision, which is exact.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

VCVTHF82PS widens E4M3 bytes to singles as VCVTBF82PS does for E5M2: the low 4, 8 or 16 bytes of an xmm register, or 32, 64 or 128 bits of memory, become 4, 8 or 16 singles under a write mask of one bit per single, with no broadcast. The conversion is exact, so MXCSR is neither read nor written and nothing is flagged; DAZ does not apply. It belongs to AVX10_V2_AUX of the ACE specification, opcode 36h with no prefix in EVEX map 5, W0. VCVTPS2HF8 goes the other way, and AVX10.2’s VCVTHF82PH widens E4M3 to halves.

What each byte becomes

E4M3, described on TDPHF8PS’s page, has no infinity: its top exponent holds numbers, so 7Eh gives 448.0 (43E00000h), and only 7Fh and FFh are NaNs. They become quiet single NaNs of their sign with all three fraction bits moved to the top of the single’s fraction, 7FF00000h and FFF00000h. The denormals 01h to 07h, from 2^-9 up, become normal singles, and 38h gives 1.0. A byte that went through VCVTPS2HF8 comes back as the E4M3 value that was chosen, so a round trip shows the rounding error directly.

In our builds

GCC 14 and Clang 23 have no option for AVX10_V2_AUX: Clang 23’s assembler and GNU as 2.44 reject the mnemonic, and ACE’s intrinsic _mm512_cvthf8_ps is missing from Clang 23’s headers. This site’s recorded cases include none of VCVTHF82PS.

Forms

Every encoding of VCVTHF82PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTHF82PS xmm {k}{z}, xmm VCVTHF82PS_XMMf32_MASKmskw_XMMhf8_AVX512EVEX.128.NP.MAP5.W0 36 /rAVX10_V2_AUX + AVX10
VCVTHF82PS xmm {k}{z}, m32 VCVTHF82PS_XMMf32_MASKmskw_MEMhf8_AVX512EVEX.128.NP.MAP5.W0 36 /rAVX10_V2_AUX + AVX10
VCVTHF82PS ymm {k}{z}, xmm VCVTHF82PS_YMMf32_MASKmskw_XMMhf8_AVX512EVEX.256.NP.MAP5.W0 36 /rAVX10_V2_AUX + AVX10
VCVTHF82PS ymm {k}{z}, m64 VCVTHF82PS_YMMf32_MASKmskw_MEMhf8_AVX512EVEX.256.NP.MAP5.W0 36 /rAVX10_V2_AUX + AVX10
VCVTHF82PS zmm {k}{z}, xmm VCVTHF82PS_ZMMf32_MASKmskw_XMMhf8_AVX512EVEX.512.NP.MAP5.W0 36 /rAVX10_V2_AUX + AVX10
VCVTHF82PS zmm {k}{z}, m128 VCVTHF82PS_ZMMf32_MASKmskw_MEMhf8_AVX512EVEX.512.NP.MAP5.W0 36 /rAVX10_V2_AUX + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a single, converted, in the same order.
VCVTHF82PS: each element widenedResult singles 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.0123456789101112131415xmm2or m128a1111111111111110k1a0a1a2a3a4a5a6a7a8a9a10a11a12a13a15zmm1

Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 bytes. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result singles 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.f32[i] = to_f32(src2.hf8[i])
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# HF8: exact, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Not run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VCVTHF82PS xmm {k}{z}, xmm/m32 VCVTHF82PS ymm {k}{z}, xmm/m64 VCVTHF82PS zmm {k}{z}, xmm/m128
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m32/64/128explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms
write masking
Memory forms
memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX10_V2_AUX_128

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_256
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_512
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More AVX10_V2_AUX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.