Instruction
VCVTNE2PS2BF16
Converts two vectors of singles into one vector of bfloat16 values, rounding to nearest even.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCVTNE2PS2BF16 xmm {k}{z}, xmm, xmm
VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 | EVEX.128.F2.0F38.W0 72 /r | AVX10.1 or AVX512_BF16 |
VCVTNE2PS2BF16 xmm {k}{z}, xmm, m128/m32bcst
VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 | EVEX.128.F2.0F38.W0 72 /r | AVX10.1 or AVX512_BF16 |
VCVTNE2PS2BF16 ymm {k}{z}, ymm, ymm
VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 | EVEX.256.F2.0F38.W0 72 /r | AVX10.1 or AVX512_BF16 |
VCVTNE2PS2BF16 ymm {k}{z}, ymm, m256/m32bcst
VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 | EVEX.256.F2.0F38.W0 72 /r | AVX10.1 or AVX512_BF16 |
VCVTNE2PS2BF16 zmm {k}{z}, zmm, zmm
VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 | EVEX.512.F2.0F38.W0 72 /r | AVX10.1 or AVX512_BF16 |
VCVTNE2PS2BF16 zmm {k}{z}, zmm, m512/m32bcst
VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 | EVEX.512.F2.0F38.W0 72 /r | AVX10.1 or AVX512_BF16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VCVTNE2PS2BF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvtne2ps_pbh
__m128bh _mm_cvtne2ps_pbh(__m128 __A, __m128 __B) |
|
_mm_mask_cvtne2ps_pbh
__m128bh _mm_mask_cvtne2ps_pbh(__m128bh __W, __mmask8 __U, __m128 __A, __m128 __B) |
|
_mm_maskz_cvtne2ps_pbh
__m128bh _mm_maskz_cvtne2ps_pbh(__mmask8 __U, __m128 __A, __m128 __B) |
|
_mm256_cvtne2ps_pbh
__m256bh _mm256_cvtne2ps_pbh(__m256 __A, __m256 __B) |
|
_mm256_mask_cvtne2ps_pbh
__m256bh _mm256_mask_cvtne2ps_pbh(__m256bh __W, __mmask16 __U, __m256 __A, __m256 __B) |
|
_mm256_maskz_cvtne2ps_pbh
__m256bh _mm256_maskz_cvtne2ps_pbh(__mmask16 __U, __m256 __A, __m256 __B) |
|
_mm512_cvtne2ps_pbh
__m512bh _mm512_cvtne2ps_pbh(__m512 __A, __m512 __B) |
|
_mm512_mask_cvtne2ps_pbh
__m512bh _mm512_mask_cvtne2ps_pbh(__m512bh __W, __mmask32 __U, __m512 __A, __m512 __B) |
|
_mm512_maskz_cvtne2ps_pbh
__m512bh _mm512_maskz_cvtne2ps_pbh(__mmask32 __U, __m512 __A, __m512 __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_BF16_128 | AVX10.1 or AVX512_BF16 | Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_BF16_256 | AVX10.1 or AVX512_BF16 | Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_BF16_512 | AVX10.1 or AVX512_BF16 | Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VBROADCASTI32X4
- VBROADCASTI32X8
- VBROADCASTI64X2
- VBROADCASTI64X4
- VBROADCASTSD
- VBROADCASTSS
- VCMPPD
- VCMPPH
- VCMPPS
- VCMPSD
- VCMPSH
- VCMPSS
- VCOMISD
- VCOMISH
- VCOMISS
- VCOMPRESSPD
- VCOMPRESSPS
- VCVTDQ2PD
- VCVTDQ2PH
- VCVTDQ2PS
- VCVTNEPS2BF16
- VCVTPD2DQ
- VCVTPD2PH
- VCVTPD2PS
- VCVTPD2QQ
- VCVTPD2UDQ
- VCVTPD2UQQ
- VCVTPH2DQ
- VCVTPH2PD
- VCVTPH2PS
- VCVTPH2PSX
- VCVTPH2QQ
- VCVTPH2UDQ
- VCVTPH2UQQ
- VCVTPH2UW
- VCVTPH2W
- VCVTPS2DQ
- VCVTPS2PD
- VCVTPS2PH
- VCVTPS2PHX
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.