VCVTNE2PS2BF16

VCVTNE2PS2BF16 rounds the singles of two registers to bfloat16 and packs them into one: the elements of the third operand fill the lower half of the result, those of the second operand the upper half. A bfloat16 is the upper 16 bits of a single, so the conversion keeps the 8-bit exponent and rounds the 23-bit fraction to 7 bits. It came with AVX512_BF16, with VCVTNEPS2BF16, which narrows one register into half of one, and VDPBF16PS, which multiplies the pairs it produces.

Which source goes low#

In C, _mm512_cvtne2ps_pbh(a, b) puts the 16 values of b in the low 16 words and those of a above them: GCC 14 and Clang 23 at -O2 compile it to vcvtne2ps2bf16 zmm0, zmm0, zmm1 with a in zmm0. To narrow 32 consecutive floats in their order, the later 16 are the first argument. Intel’s optimization manual converts AMX results this way, two blocks of floats into whole 64-byte lines of bfloat16, passing the second block first (Section 20.11.4, Example 20-23). Unlike VPACKSSDW, the instruction does not interleave its sources by 128-bit lane, so no permute has to follow.

Neither compiler uses it for a plain loop: with -march=znver5, Clang 23 narrows an array of floats to __bf16 with the one-source VCVTNEPS2BF16, and GCC 14 calls the library routine __truncsfbf2 for each element.

Fixed rounding#

The instruction never reads or writes MXCSR and raises no exception. Zen 5’s recorded cases show what that means:

• It always rounds to nearest even: with MXCSR.RC set to round toward zero, 3F808000h (1 + 2^-8, a tie) gave 3F80h, and the largest single, 7F7FFFFFh, gave infinity, 7F80h.
• Denormal inputs become zeros of their sign, with DAZ clear: 007FC000h, which would otherwise round to the smallest normal bfloat16, gave 0000h, and 80400000h gave 8000h.
• NaNs come out quiet, keeping the top 7 bits of their fraction: the signaling NaN 7F812345h gave 7FC1h, and FF800001h, whose payload lies only in the dropped bits, gave FFC0h. With the invalid-operation exception unmasked, no #XM followed.

AMD’s Zen 5 guide lists the xmm form as one macro-op with a latency of 3 cycles, and the ymm and zmm forms as two, with 6 and 7.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        if i < VL // 32:
            x = src3.f32[i]
        else:
            x = zmm2.f32[i - VL // 32]
        zmm1.bf16[i] = to_bf16_ne(x)
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTNE2PS2BF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX

All 686 AVX10.1 instructions