VCVTNEEPH2PS

VCVTNEEPH2PS reads 128 or 256 bits of half-precision (FP16) values from memory and widens the even-numbered ones, elements 0, 2, 4 and so on, to singles, four into an XMM register or eight into a YMM one; the bits above are cleared. VCVTNEOPH2PS takes the odd elements. It is the FP16 twin of VCVTNEEBF162PS, with the same memory-only operand, which Crestmont, Intel’s optimization manual says, converts in its load pipelines.

Beside VCVTPH2PS#

VCVTPH2PS of F16C does the same conversion for consecutive halves, from a register or memory. Both are exact, since every FP16 value has a single, and both turn a denormal into the normal single it equals, ignoring DAZ. The difference is in what they report: VCVTPH2PS sets IE in MXCSR for a signaling NaN and can raise #XM for it, while VCVTNEEPH2PS reports no exception and neither reads nor writes MXCSR. Intel’s entry calls a helper, convert_fp16_to_fp32, that the manual never defines, so whether a signaling NaN comes out quiet is not spelled out; the Operation section here makes it quiet, as VCVTPH2PS does, without a flag.

In compiled code#

GCC 14 and Clang 23 compile _mm_cvtneeph_ps(p) with -mavxneconvert to vcvtneeph2ps xmm0, xmmword ptr [rdi]. They do not reach for it otherwise in our builds. At -march=sierraforest, a loop multiplying pairs, o[i] = (float)h[2*i] * (float)h[2*i+1], becomes in Clang 23 a VPBLENDW and VPACKUSDW for the even halves and a VPSRLD and VPACKUSDW for the odd ones, then VCVTPH2PS on each, where this instruction and its odd twin would load and convert in one step each; GCC 14 converts element by element with VPINSRW and VCVTPH2PS. With -mavxneconvert alone, which brings no F16C, both call __extendhfsf2 for every element. The encoding is VEX.66.0F38.W0 B0. Zen 5 lacks AVX-NE-CONVERT.

In the optimization guide

What the optimization guide says about VCVTNEEPH2PS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont widens BF16 and FP16 to single precision in the load pipelines, using no vector port.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    ymm1.f32[i] = to_f32_ne(mem.f16[2 * i])
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTNEEPH2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-NE-CONVERT instructions

• VBCSTNEBF162PS
• VBCSTNESH2PS
• VCVTNEEBF162PS
• VCVTNEOBF162PS
• VCVTNEOPH2PS
• VCVTNEPS2BF16