VCVTNEOBF162PS

VCVTNEOBF162PS reads 128 or 256 bits of bfloat16 values from memory and widens the odd-numbered ones, elements 1, 3, 5 and so on, to singles: each doubleword of the destination gets the high word of the matching doubleword in memory. It is the other half of VCVTNEEBF162PS, whose page covers what the two share: the source is always memory, which Crestmont widens in its load pipelines; the conversion is exact and puts the 16 bits above 16 zeros, so denormals and signaling NaNs come through as they are; no exception, no MXCSR; and the bits above the vector are cleared.

The cheapest of the four#

For an odd element the bfloat16 value already sits in the upper half of its doubleword, so the single it becomes is that doubleword with its low 16 bits cleared, an AND with FFFF0000h on each element. A loop summing pairs, o[i] = (float)b[2*i] + (float)b[2*i+1], shows both halves in our builds: Clang 23 at -O2 with -mavxneconvert gets the even elements with VPSLLD by 16 and the odd ones with a VPBLENDW against zero, from ordinary loads, and does not use this instruction; GCC 14 calls __extendbfsf2 for each element. What the instruction saves is the separate ALU step, done in the load instead.

The encoding is VEX.F2.0F38.W0 B0, at 128 and 256 bits, and the intrinsics are _mm_cvtneobf16_ps and _mm256_cvtneobf16_ps, which take a pointer; GCC 14 and Clang 23 compile them with -mavxneconvert to the instruction with that pointer as its operand. Zen 5 lacks AVX-NE-CONVERT.

In the optimization guide

What the optimization guide says about VCVTNEOBF162PS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont widens BF16 and FP16 to single precision in the load pipelines, using no vector port.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = mem.bf16[2 * i + 1]
    ymm1.f32[i] = to_f32_ne(a)
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTNEOBF162PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-NE-CONVERT instructions

• VBCSTNEBF162PS
• VBCSTNESH2PS
• VCVTNEEBF162PS
• VCVTNEEPH2PS
• VCVTNEOPH2PS
• VCVTNEPS2BF16