VCVTNEOPH2PS

VCVTNEOPH2PS reads 128 or 256 bits of half-precision (FP16) values from memory and widens the odd-numbered ones, elements 1, 3, 5 and so on, to singles: each doubleword of the destination comes from the high word of the matching doubleword in memory. Four results fill an XMM register, eight a YMM one, and the bits above are cleared. It is the odd half of VCVTNEEPH2PS, whose page compares the pair with VCVTPH2PS: the conversion is exact, a denormal becomes a normal single whatever DAZ says, and nothing is reported to MXCSR or read from it.

Pairs of halves#

Data that holds FP16 values in pairs, such as the real and imaginary parts of complex numbers, which AVX512-FP16’s complex multiplies take in that layout, splits into two vectors of singles with one even and one odd load. Without them, the halves must first be separated: a shift right by 16 in each doubleword, then a pack to consecutive words, as Clang 23’s code at -march=sierraforest does in our builds before its VCVTPH2PS.

Encoding#

The instruction is VEX.NP.0F38.W0 B0, without a prefix; the same opcode with 66 is the even form, and with F3 and F2 the bfloat16 ones. ModRM must name memory. The intrinsics _mm_cvtneoph_ps and _mm256_cvtneoph_ps take a pointer, and GCC 14 and Clang 23 compile _mm256_cvtneoph_ps(p) with -mavxneconvert to vcvtneoph2ps ymm0, ymmword ptr [rdi]. Intel lists AVX-NE-CONVERT for Sierra Forest, Grand Ridge, Arrow Lake H and Diamond Rapids; Zen 5 lacks it.

In the optimization guide

What the optimization guide says about VCVTNEOPH2PS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont widens BF16 and FP16 to single precision in the load pipelines, using no vector port.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = mem.f16[2 * i + 1]
    ymm1.f32[i] = to_f32_ne(a)
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTNEOPH2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-NE-CONVERT instructions

• VBCSTNEBF162PS
• VBCSTNESH2PS
• VCVTNEEBF162PS
• VCVTNEEPH2PS
• VCVTNEOBF162PS
• VCVTNEPS2BF16