x86-64.net

Instruction

VCVTNEPS2BF16

Converts packed single-precision values to bfloat16, rounding to nearest even with denormals flushed to zero and without consulting MXCSR.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTNEPS2BF16 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTNEPS2BF16 xmm, xmm VCVTNEPS2BF16_XMMbf16_XMMf32VEX.128.F3.0F38.W0 72 /rAVX_NE_CONVERT
VCVTNEPS2BF16 xmm, m128 VCVTNEPS2BF16_XMMbf16_MEMf32_VL128VEX.128.F3.0F38.W0 72 /rAVX_NE_CONVERT
VCVTNEPS2BF16 xmm, ymm VCVTNEPS2BF16_XMMbf16_YMMf32VEX.256.F3.0F38.W0 72 /rAVX_NE_CONVERT
VCVTNEPS2BF16 xmm, m256 VCVTNEPS2BF16_XMMbf16_MEMf32_VL256VEX.256.F3.0F38.W0 72 /rAVX_NE_CONVERT
VCVTNEPS2BF16 xmm {k}{z}, xmm VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512EVEX.128.F3.0F38.W0 72 /rAVX10.1 or AVX512_BF16
VCVTNEPS2BF16 xmm {k}{z}, m128/m32bcst VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128EVEX.128.F3.0F38.W0 72 /rAVX10.1 or AVX512_BF16
VCVTNEPS2BF16 xmm {k}{z}, ymm VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512EVEX.256.F3.0F38.W0 72 /rAVX10.1 or AVX512_BF16
VCVTNEPS2BF16 xmm {k}{z}, m256/m32bcst VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256EVEX.256.F3.0F38.W0 72 /rAVX10.1 or AVX512_BF16
VCVTNEPS2BF16 ymm {k}{z}, zmm VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512EVEX.512.F3.0F38.W0 72 /rAVX10.1 or AVX512_BF16
VCVTNEPS2BF16 ymm {k}{z}, m512/m32bcst VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512EVEX.512.F3.0F38.W0 72 /rAVX10.1 or AVX512_BF16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTNEPS2BF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtneps_avx_pbh __m128bh _mm_cvtneps_avx_pbh(__m128 __A)

VCVTNEPS2BF16 xmm, xmm VEX.128 -mavxneconvert

_mm_cvtneps_pbh __m128bh _mm_cvtneps_pbh(__m128 A)

VCVTNEPS2BF16 xmm, xmm EVEX.128 -mavx512vl -mavx512bf16

_mm_mask_cvtneps_pbh __m128bh _mm_mask_cvtneps_pbh(__m128bh __W, __mmask8 __U, __m128 __A)

VCVTNEPS2BF16 xmm {k}, xmm EVEX.128 -mavx512vl -mavx512bf16

_mm_maskz_cvtneps_pbh __m128bh _mm_maskz_cvtneps_pbh(__mmask8 __U, __m128 __A)

VCVTNEPS2BF16 xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512bf16

_mm256_cvtneps_avx_pbh __m128bh _mm256_cvtneps_avx_pbh(__m256 __A)

VCVTNEPS2BF16 xmm, ymm VEX.256 -mavxneconvert

_mm256_cvtneps_pbh __m128bh _mm256_cvtneps_pbh(__m256 A)

VCVTNEPS2BF16 xmm, ymm EVEX.256 -mavx512vl -mavx512bf16

_mm256_mask_cvtneps_pbh __m128bh _mm256_mask_cvtneps_pbh(__m128bh __W, __mmask8 __U, __m256 __A)

VCVTNEPS2BF16 xmm {k}, ymm EVEX.256 -mavx512vl -mavx512bf16

_mm256_maskz_cvtneps_pbh __m128bh _mm256_maskz_cvtneps_pbh(__mmask8 __U, __m256 __A)

VCVTNEPS2BF16 xmm {k}{z}, ymm EVEX.256 -mavx512vl -mavx512bf16

_mm512_cvtneps_pbh __m256bh _mm512_cvtneps_pbh(__m512 __A)

VCVTNEPS2BF16 ymm, zmm EVEX.512 -mavx512bf16

_mm512_mask_cvtneps_pbh __m256bh _mm512_mask_cvtneps_pbh(__m256bh __W, __mmask16 __U, __m512 __A)

VCVTNEPS2BF16 ymm {k}, zmm EVEX.512 -mavx512bf16

_mm512_maskz_cvtneps_pbh __m256bh _mm512_maskz_cvtneps_pbh(__mmask16 __U, __m512 __A)

VCVTNEPS2BF16 ymm {k}{z}, zmm EVEX.512 -mavx512bf16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX_NE_CONVERT

AVX_NE_CONVERT
CPUID.(EAX=07H,ECX=1):EDX[5] AVX_NE_CONVERT

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest
AVX512_BF16_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_BF16
CPUID.(EAX=07H,ECX=1):EAX[5] AVX512_BF16

Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_BF16_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_BF16
CPUID.(EAX=07H,ECX=1):EAX[5] AVX512_BF16

Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_BF16_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_BF16
CPUID.(EAX=07H,ECX=1):EAX[5] AVX512_BF16

Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX-NE-CONVERT instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.