VCVTNEPS2BF16

VCVTNEPS2BF16 rounds each single of a register or of memory to bfloat16, the upper 16 bits of a single, and packs the results into the low half of the destination: 4 singles of an XMM source become 4 words of an XMM register, 8 of a YMM source fill an XMM register and 16 of a ZMM source a YMM one, and the bits above are cleared. It is the one-source form of VCVTNE2PS2BF16, whose page covers the fixed rounding: to nearest even whatever MXCSR says, denormal inputs as zeros of their sign, NaNs made quiet, MXCSR neither read nor written. It has two encodings: the EVEX one of AVX512_BF16, with a write mask and a broadcast, and a VEX one at 128 and 256 bits from AVX-NE-CONVERT, which the assembler marks {vex}.

Recorded on Zen 5#

The 31 cases, all EVEX, agree with the SDM’s conversion routine, which adds 7FFFh plus the lowest kept bit to the single and keeps the upper half.

• Ties. 3F808000h gave 3F80h and 3F818000h gave 3F82h, each to the even neighbor, and 3F80C000h, above the tie, gave 3F81h.
• Overflow. 7F7F8000h, a tie below infinity, gave 7F80h, as did the largest single, while 7F7F0000h stayed 7F7Fh.
• Exceptions. With MXCSR 0, every exception unmasked, the signaling NaN 7F812345h gave 7FC1h without a fault, and MXCSR stayed 0.
• Masks. Zeroing masking cleared the words left out, and a broadcast of 3F818000h gave 3F82h in every word selected.

In compiled code#

At -O2 with -march=znver5, Clang 23 converts float to __bf16 with VCVTNEPS2BF16, one value or, in a loop, 8 at a time from YMM registers; with -mavxneconvert it uses the VEX form. GCC 14 calls __truncsfbf2 for each element in every case, and emits the instruction only for intrinsics such as _mm512_cvtneps_pbh. The two differ on denormals: 007FC000h gives 0 here, where an exact rounding gives 0080h, the smallest normal bfloat16.

AMD’s Zen 5 latency spreadsheet gives the XMM source one macro-op on pipe FP2 or FP3 and 3 cycles, and the YMM and ZMM sources two macro-ops with 6 and 7 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = src2.f32[i]
        ymm1.bf16[i] = to_bf16_ne(a)
    elif zeroing:
        ymm1.bf16[i] = 0
    # else: ymm1.bf16[i] keeps its value
for i in range(VL // 32, 8):
    ymm1.w[i] = 0
# m32bcst: src2.f32[i] is the m32 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

VEX forms

always rounds to nearest even; denormal inputs read as zero; denormal results flushed to zero

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTNEPS2BF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-NE-CONVERT instructions

• VBCSTNEBF162PS
• VBCSTNESH2PS
• VCVTNEEBF162PS
• VCVTNEEPH2PS
• VCVTNEOBF162PS
• VCVTNEOPH2PS

More AVX10.1 instructions

• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ

All 686 AVX10.1 instructions