VCVTPD2DQ

VCVTPD2DQ converts doubles to signed doublewords, rounding as MXCSR.RC says, into a register half as wide as the source: two doubles from an xmm register or 16 bytes into the low half of an xmm register with VEX or EVEX, four into a whole xmm register, and with EVEX eight from a zmm register into a ymm register; the destination is zeroed above the result. CVTPD2DQ covers the rounding at the edge of the range, and VCVTTPD2DQ, the truncating twin, the AT&T suffixes x and y that a memory source needs. VEX needs AVX, with no alignment requirement; EVEX needs AVX-512F (AVX512VL below 512 bits) or AVX10.1 and adds a mask bit per doubleword, a broadcast double, and a rounding mode for a zmm register source.

Recorded on Zen 5#

• vcvtpd2dq xmm12, ymm6, with MXCSR DF80h asking for rounding up, turned 3, 0.1, 2^31 and -2^31 into 3, 1, 80000000h and 80000000h: 0.1 went up to 1, 2^31 does not fit and gave the integer indefinite, and -2^31 is the same bits as a real result. IE and PE were set.
• vcvtpd2dq ymm0{k4}, zmm31, {rz-sae}, the low byte of K4 E5h, wrote elements 0, 2, 5, 6 and 7: +0.0 gave 0, and +infinity, a quiet NaN and two signaling NaNs gave 80000000h. MXCSR 6600h unmasks the invalid exception, yet nothing was raised or flagged.
• A broadcast 2,147,483,647.5, {1to2} in AT&T syntax, became 7FFFFFFFh in both elements under rounding toward zero.

In compiled code#

In our builds at -O2, out[i] = (int)rint(in[i]) over global arrays is where the two compilers part. With -march=x86-64-v3, Clang 23 converts each 32 bytes with one vcvtpd2dq xmm0, ymmword ptr [...], since rint rounds as MXCSR says; GCC 14 rounds with VROUNDPD and immediate 4, the current mode, and then truncates with VCVTTPD2DQ, and at -v4 does the same with VRNDSCALEPD on zmm registers.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows the same figures: one macro-op and 3 cycles from an xmm source, two macro-ops and 6 cycles from a ymm source, and 7 cycles from a zmm one.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        ymm1.d[i] = cvt_int(src2.f64[i], 32)
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# m64bcst: src2.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPD2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128

All 253 AVX instructions

More AVX10.1 instructions

• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ

All 686 AVX10.1 instructions