VCVTPD2PH

VCVTPD2PH narrows doubles to half precision: 2, 4 or 8 of them from an XMM, YMM or ZMM register or memory into the low 32, 64 or 128 bits of an XMM register, with the rest cleared. It rounds by MXCSR.RC or by an {er} mode on the 512-bit register form, takes a double broadcast from memory and a write mask, and can overflow to infinity past 65504 or underflow to a denormal or zero. The opcode is that of VCVTPD2PS, 5Ah with the 66 prefix, in EVEX map 5 with W1; VCVTPH2PD is the way back and VCVTSD2SH the scalar form.

One rounding, not two#

Intel’s entry says that DAZ applies to the double inputs and that the half results are never flushed to zero, as for VCVTPS2PHX. Narrowing in one step matters, because going through a single rounds twice. Take 1 + 2^-11 + 2^-40, just above halfway between the halves 1 and 1 + 2^-10, so that the correctly rounded half is 1 + 2^-10, which VCVTPD2PH gives. As a single it first becomes 1 + 2^-11, since 2^-40 is far below a single’s spacing of 2^-23 at 1; that single is exactly halfway between the two halves, and round to nearest even then gives 1.

In our builds#

GCC 14.2.0 and Clang 23.1.2, at -O2 with -march=x86-64-v4 -mavx512fp16, compile h[i] = d[i] over global double and _Float16 arrays of 1024 elements differently. Clang converts with VCVTPD2PH from YMM loads, joining the XMM results with VINSERTF128 and VUNPCKLPD. GCC goes through singles, VCVTPD2PS and then VCVTPS2PHX, at -O2 and -O3 and also with -march=sapphirerapids, so for the value above its loop stores 1 where the correctly rounded result is 1 + 2^-10. The count decides, not how the arrays are passed: pointer parameters give the same two steps for 1024 elements, while at -O2 a count known only at run time, or one that leaves a remainder such as 1,001, keeps GCC’s loop scalar with VCVTSD2SH, rounding once. At -O3 GCC takes the two steps for any count and converts the remainder with VCVTSD2SH, the instruction it also uses for a single double. _mm512_cvtpd_ph gives VCVTPD2PH in both compilers, and Clang folds _mm512_set1_pd(*p) into a {1to8} broadcast where GCC uses VBROADCASTSD. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPD2PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.f16[i] = to_f16(src2.f64[i])
    elif zeroing:
        xmm1.f16[i] = 0
    # else: xmm1.f16[i] keeps its value
for i in range(VL // 64, 8):
    xmm1.w[i] = 0
# m64bcst: src2.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPD2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ

All 686 AVX10.1 instructions