x86-64.net

Instruction

VCVTPD2PS

Converts packed doubles to singles, rounding as MXCSR or the instruction selects.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTPD2PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTPD2PS xmm, m128 VCVTPD2PS_XMMdq_MEMdqVEX.128.66.0F.WIG 5A /rAVX
VCVTPD2PS xmm, xmm VCVTPD2PS_XMMdq_XMMdqVEX.128.66.0F.WIG 5A /rAVX
VCVTPD2PS xmm, m256 VCVTPD2PS_XMMdq_MEMqqVEX.256.66.0F.WIG 5A /rAVX
VCVTPD2PS xmm, ymm VCVTPD2PS_XMMdq_YMMqqVEX.256.66.0F.WIG 5A /rAVX
VCVTPD2PS ymm {k}{z}, zmm, {er} VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512EVEX.512.66.0F.W1 5A /rAVX10.1 or AVX512F
VCVTPD2PS ymm {k}{z}, m512/m64bcst VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512EVEX.512.66.0F.W1 5A /rAVX10.1 or AVX512F
VCVTPD2PS xmm {k}{z}, xmm VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128EVEX.128.66.0F.W1 5A /rAVX10.1 or AVX512F + AVX512VL
VCVTPD2PS xmm {k}{z}, m128/m64bcst VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128EVEX.128.66.0F.W1 5A /rAVX10.1 or AVX512F + AVX512VL
VCVTPD2PS xmm {k}{z}, ymm VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256EVEX.256.66.0F.W1 5A /rAVX10.1 or AVX512F + AVX512VL
VCVTPD2PS xmm {k}{z}, m256/m64bcst VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256EVEX.256.66.0F.W1 5A /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPD2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtpd_ps __m128 _mm_cvtpd_ps(__m128d __a)

VCVTPD2PS xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_cvtpd_ps __m128 _mm_mask_cvtpd_ps(__m128 __W, __mmask8 __U, __m128d __A)

VCVTPD2PS xmm {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_cvtpd_ps __m128 _mm_maskz_cvtpd_ps(__mmask8 __U, __m128d __A)

VCVTPD2PS xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_cvtpd_ps __m128 _mm256_cvtpd_ps(__m256d __a)

VCVTPD2PS xmm, ymm VEX.256 -mavx

_mm256_mask_cvtpd_ps __m128 _mm256_mask_cvtpd_ps(__m128 __W, __mmask8 __U, __m256d __A)

VCVTPD2PS xmm {k}, ymm EVEX.256 -mavx512vl

_mm256_maskz_cvtpd_ps __m128 _mm256_maskz_cvtpd_ps(__mmask8 __U, __m256d __A)

VCVTPD2PS xmm {k}{z}, ymm EVEX.256 -mavx512vl

_mm512_cvt_roundpd_ps __m256 _mm512_cvt_roundpd_ps(__m512d A, const int R)

VCVTPD2PS ymm, zmm, {er} EVEX.512 -mavx512f

_mm512_cvtpd_ps __m256 _mm512_cvtpd_ps(__m512d __A)

VCVTPD2PS ymm, zmm EVEX.512 -mavx512f

_mm512_cvtpd_pslo __m512 _mm512_cvtpd_pslo(__m512d __A)

VCVTPD2PS ymm, zmm EVEX.512 -mavx512f

_mm512_mask_cvt_roundpd_ps __m256 _mm512_mask_cvt_roundpd_ps(__m256 W, __mmask8 U, __m512d A, const int R)

VCVTPD2PS ymm {k}, zmm, {er} EVEX.512 -mavx512f

_mm512_mask_cvtpd_ps __m256 _mm512_mask_cvtpd_ps(__m256 __W, __mmask8 __U, __m512d __A)

VCVTPD2PS ymm {k}, zmm EVEX.512 -mavx512f

_mm512_mask_cvtpd_pslo __m512 _mm512_mask_cvtpd_pslo(__m512 __W, __mmask8 __U, __m512d __A)

VCVTPD2PS ymm {k}, zmm EVEX.512 -mavx512f

_mm512_maskz_cvt_roundpd_ps __m256 _mm512_maskz_cvt_roundpd_ps(__mmask8 U, __m512d A, const int R)

VCVTPD2PS ymm {k}{z}, zmm, {er} EVEX.512 -mavx512f

_mm512_maskz_cvtpd_ps __m256 _mm512_maskz_cvtpd_ps(__mmask8 __U, __m512d __A)

VCVTPD2PS ymm {k}{z}, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.