VCVTPD2PS

VCVTPD2PS narrows doubles to singles, rounded: a ymm register or 32 bytes into an xmm register with VEX, a zmm into a ymm with EVEX. CVTPD2PS covers what narrowing does to each value, the half-width result, the x and y suffixes AT&T syntax needs for memory operands, and how compilers join two results into one store. What the EVEX forms add is control over the rounding and the exceptions of each instruction.

Rounding given in the instruction#

With a zmm source register, {rn-sae}, {rd-sae}, {ru-sae} or {rz-sae} replaces MXCSR’s rounding and reports no exception. The cases recorded on Zen 5 with {rd-sae}, MXCSR asking for the nearest:

• 0.1 became 3DCCCCCCH, where rounding to nearest gives 3DCCCCCDH;
• -2,147,483,649 became CF000001H, the single below -2^31;
• 10^300 became 7F7FFFFFH, the largest single, as an overflow rounded down does not reach infinity, and 10^-300 became +0.

With {rz-sae}, -1.7 × 10^44 likewise gave the most negative finite single, FF7FFFFFH.

Nothing reported#

With every exception unmasked (MXCSR 0) and {rn-sae}, Zen 5 converted signaling NaNs, the smallest double denormal and -1.1 × 10^-308 without a fault, and MXCSR stayed 0: the NaNs came back quiet, the tiny values as zeros of their sign. Without the rounding operand, the same instruction raised #XM for a signaling NaN.

A narrowed NaN keeps only the top of its payload: 7FF0000000012345H became 7FC00000H, the payload bits below the single’s 23 lost. VCVTPS2PD shows the widening side.

Masks per single#

A write mask has a bit per result single, eight for a zmm source. In vcvtpd2ps ymm24{k4}, zmm3, {rd-sae}, K4’s low byte DDH left elements 1 and 5 of YMM24 as they were.

In our builds at -O2 for -march=znver5, Clang 23 converts arrays from memory zmm to ymm, while for x86-64-v3 and x86-64-v4 it stays with ymm to xmm.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        ymm1.f32[i] = to_f32(src2.f64[i])
    elif zeroing:
        ymm1.f32[i] = 0
    # else: ymm1.f32[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# m64bcst: src2.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPD2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS

All 253 AVX instructions

More AVX10.1 instructions

• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD

All 686 AVX10.1 instructions