VCVTPD2QQ

VCVTPD2QQ converts each double of an XMM, YMM or ZMM register, or of memory, to a signed quadword, rounding as MXCSR.RC says or, in the 512-bit register form, as its {er} operand says. It came with AVX512DQ, together with the truncating VCVTTPD2QQ, whose page covers the range: out-of-range values, NaNs and infinities give the integer indefinite, 8000000000000000h, and set IE. VCVTPD2DQ is the same for doublewords.

Recorded on Zen 5#

• MXCSR decides. With MXCSR FFC0h, rounding toward zero, a broadcast 2.5 became 2 in the five elements K4 selects, and PE was set. Under {ru-sae} with MXCSR 6600h, which asks for rounding toward zero and unmasks PE, 2.5 became 3 and -0.5 became 0, with no exception and no flag.
• Rounding down (BF80h) turned 0.1 into 0 and set PE, while 2^31 - 1 converted exactly.
• NaNs. Quiet and signaling NaNs gave the integer indefinite and set IE; a signaling NaN in an element the mask left out did not change the element.
• Denormals. Under DAZ with rounding up, MXCSR 5FC0h, the largest positive denormal became 0, not 1, and PE stayed clear.

In compiled code#

C’s cast truncates, so out[i] = (long)in[i] gives VCVTTPD2QQ. lrint and llrint round as MXCSR says, which is this instruction, but they may set errno. At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 call the library function for each element; with -fno-math-errno both convert out[i] = lrint(in[i]) with VCVTPD2QQ, GCC on ZMM and Clang on YMM registers, and a single lrint with VCVTSD2SI. For (long)rint(in[i]) GCC with -fno-math-errno also uses VCVTPD2QQ, and otherwise rounds with VRNDSCALEPD and truncates with VCVTTPD2QQ; Clang always rounds with VROUNDPD first. The intrinsic _mm512_cvt_roundpd_epi64 with _MM_FROUND_TO_NEAREST_INT gives the {rn-sae} form.

AMD’s Zen 5 latency spreadsheet gives VCVTPD2QQ 3 cycles at every width, two per cycle on pipes FP2 and FP3, as VCVTQQ2PD. Zen 5’s 6 recorded cases cover the register, memory and broadcast forms at all three widths and the rounding operand.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = cvt_int(src2.f64[i], 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPD2QQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH

All 686 AVX10.1 instructions