VCVTPD2UDQ

VCVTPD2UDQ converts doubles to unsigned doublewords, rounding as MXCSR.RC or an {er} override says: 8 doubles of a ZMM register become 8 doublewords in a YMM register, 4 fill an XMM register and 2 fill its low 64 bits, and the rest of the destination is cleared. It is the rounding form of VCVTTPD2UDQ, whose page covers the halved width, and the unsigned partner of VCVTPD2DQ, with the range 0 to 2^32 - 1 and FFFFFFFFh as the indefinite value. It came with AVX512F; the 512-bit register form takes {er}.

Recorded on Zen 5#

• Negative but rounding to zero. -1.5 from a broadcast, with RC truncating, gave FFFFFFFFh and set IE, since it truncates to -1. In another case -0.0 gave 0 and positive infinity FFFFFFFFh.
• No flag under an override. With {ru-sae} and IE unmasked, negative infinity and two signaling NaNs gave FFFFFFFFh without a fault or a flag; 0.0 gave 0.
• Masked off. vcvtpd2udq xmm7{k6}{z}, ymm12 converted only 2.0, to 2; the -1.0 left out by the mask set no flag.
• The smallest normal double gave 0 and set PE.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile _mm512_cvtpd_epu32 and _mm256_cvtpd_epu32 to VCVTPD2UDQ from ZMM and YMM registers. A conversion in C truncates and so uses VCVTTPD2UDQ.

AMD’s Zen 5 latency spreadsheet gives the XMM source one macro-op and 3 cycles, and the YMM and ZMM sources two macro-ops, with 6 and 7 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        ymm1.d[i] = cvt_uint(a, 32)
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# m64bcst: src2.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPD2UDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS

All 686 AVX10.1 instructions