VCVTPD2UQQ

VCVTPD2UQQ converts each double of an XMM, YMM or ZMM register, or of memory, to an unsigned quadword, rounding as MXCSR.RC says or, in the 512-bit register form, as its {er} operand says. It is the unsigned partner of VCVTPD2QQ, which came with it in AVX512DQ, and the rounding form of VCVTTPD2UQQ. The range is 0 to 2^64 - 1 after rounding: a negative value that does not round to 0, a value of 2^64 or more, a NaN or an infinity gives FFFFFFFFFFFFFFFFh and sets IE. VCVTPD2UDQ does the same for doublewords.

Recorded on Zen 5#

• Rounding up. With MXCSR rounding up, 0.5 gave 1, and -0.5 gave 0, a valid result since it rounds to zero; PE was set.
• Rounding down. -1.5 became -2, out of range, and gave FFFFFFFFFFFFFFFFh with IE.
• An override. vcvtpd2uqq zmm14{k4}, zmm8, {rn-sae}, with IE unmasked in MXCSR, gave FFFFFFFFFFFFFFFFh for -2^63 and -2^32, converted 43DFFFFFE0000000h exactly to 7FFFFF8000000000h, and gave 0 for +0 and -0, with no fault and no flag.
• Masked off. A broadcast signaling NaN in elements that K1 leaves out gave zeros under {z} and set no flag: masked elements raise no exception.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile _mm512_cvtpd_epu64 to VCVTPD2UQQ. Neither uses it for C: a loop of (uint64_t)rint(d[i]) rounds first, with VRNDSCALEPD in GCC and VROUNDPD in Clang, and then truncates with VCVTTPD2UQQ.

AMD’s Zen 5 latency spreadsheet gives every width one macro-op on pipe FP2 or FP3 and 3 cycles, as for VCVTPD2QQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        zmm1.q[i] = cvt_uint(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPD2UQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH

All 686 AVX10.1 instructions