VCVTPH2BF8

VCVTPH2BF8 rounds each half-precision value to the 8-bit E5M2 format (a sign, 5 exponent bits and 2 fraction bits, which the mnemonics call BF8), to nearest even, and packs the bytes into the low half of the destination: the 32 halves of a zmm register give 32 bytes in a ymm register, and the 8 halves of an xmm register the low 8 bytes of an xmm register. The bits above the result are cleared. It belongs to AVX10.2, opcode 74h with the F3 prefix in EVEX map 0F38, and takes a write mask with one bit per result byte and a broadcast half. VCVTPH2BF8S saturates instead of overflowing, and VCVT2PH2BF8S’s page shows how the forms with two sources fill a whole register.

FP16’s upper byte#

E5M2 keeps the half’s 5-bit exponent and its bias of 15, so the conversion only rounds away the low 8 fraction bits and keeps the upper byte. Denormal halves need nothing special, which is why the instruction ignores DAZ and FTZ; it does not read MXCSR’s rounding control either, and it sets no flag and raises no exception. A NaN keeps its upper byte with bit 1, E5M2’s quiet bit, set, and an infinity stays infinite.

The largest finite E5M2 value is 57,344 (1.75 × 2^15), and the next step up would be 2^16, so halves from 61,440, the midpoint, become infinity: at the tie, infinity’s fraction 00 is the even one. FP16’s own largest value, 65,504, becomes infinity too.

In our builds#

GCC 14 rejects -mavx10.2. Clang 23 compiles _mm512_cvtph_bf8(a) to vcvtph2bf8 ymm0, zmm0, and a half splatted with _mm512_set1_ph from memory to the broadcast form, vcvtph2bf8 ymm0, word ptr [rdi]{1to32}; the masked form loads its 32-bit mask with KMOVD. No instruction goes back the other way, since each byte is simply the top of a half: _mm512_cvtbf8_ph compiles to VPMOVZXBW and vpsllw zmm0, zmm0, 8. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        ymm1.bf8[i] = to_bf8(src2.f16[i])
    elif zeroing:
        ymm1.bf8[i] = 0
    # else: ymm1.bf8[i] keeps its value
for i in range(VL // 16, 16):
    ymm1.b[i] = 0
# m16bcst: src2.f16[i] is the m16 for every i
# BF8: to nearest even, denormals kept, no flags; MXCSR unused
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2BF8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions