VCVTPH2DQ

VCVTPH2DQ converts halves to signed doublewords, rounding by MXCSR.RC or, on the 512-bit register form, by an {er} mode in the instruction. The source is half as wide as the destination: 16 halves from a YMM register or 32 bytes of memory fill a ZMM register, 8 fill a YMM register and 4, read from 64 bits, fill an XMM register. It is the half-precision form of VCVTPS2DQ, with its opcode, 5Bh with the 66 prefix, in EVEX map 5; the truncating form is VCVTTPH2DQ and the way back VCVTDQ2PH.

Only NaN and infinity fail#

A finite half is at most 65504 in magnitude, so every one of them fits a doubleword after rounding, and the indefinite value 80000000h, which Intel’s entry returns with IE when the invalid exception is masked, can come only from a NaN or an infinity; no finite half converts to it. The precision flag is set whenever a fraction is dropped. A half can be broadcast from memory to every element ({1to16} on the ZMM form), and a write mask merges or zeroes doublewords.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16 -fno-math-errno, Clang 23 compiles a[i] = (int)rintf(h[i]) over a _Float16 array to VCVTPH2DQ on XMM registers: the half is exact as a single, so rounding it there and truncating equals one rounding conversion. GCC 14 widens with VCVTPH2PSX, rounds with VRNDSCALEPS and truncates with VCVTTPS2DQ, or uses VCVTPS2DQ after the widening with -ffast-math. For _mm512_cvtph_epi32(_mm256_set1_ph(*p)), Clang folds the broadcast into word ptr [rdi]{1to16} and GCC loads it with VPBROADCASTW first. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPH2DQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = cvt_int(src2.f16[i], 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI

All 686 AVX10.1 instructions