Instruction
VCVTPH2HF8
Converts packed half-precision values to E4M3 FP8, rounding to nearest even.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCVTPH2HF8 xmm {k}{z}, xmm
VCVTPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512 | EVEX.128.F3.MAP5.W0 18 /r | AVX10.2 or AVX10_V1_AUX |
VCVTPH2HF8 xmm {k}{z}, m128/m16bcst
VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128 | EVEX.128.F3.MAP5.W0 18 /r | AVX10.2 or AVX10_V1_AUX |
VCVTPH2HF8 xmm {k}{z}, ymm
VCVTPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512 | EVEX.256.F3.MAP5.W0 18 /r | AVX10.2 or AVX10_V1_AUX |
VCVTPH2HF8 xmm {k}{z}, m256/m16bcst
VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256 | EVEX.256.F3.MAP5.W0 18 /r | AVX10.2 or AVX10_V1_AUX |
VCVTPH2HF8 ymm {k}{z}, zmm
VCVTPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512 | EVEX.512.F3.MAP5.W0 18 /r | AVX10.2 or AVX10_V1_AUX |
VCVTPH2HF8 ymm {k}{z}, m512/m16bcst
VCVTPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512 | EVEX.512.F3.MAP5.W0 18 /r | AVX10.2 or AVX10_V1_AUX |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VCVTPH2HF8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvtph_hf8
__m128i _mm_cvtph_hf8(__m128h __A) |
|
_mm_mask_cvtph_hf8
__m128i _mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) |
|
_mm_maskz_cvtph_hf8
__m128i _mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) |
|
_mm256_cvtph_hf8
__m128i _mm256_cvtph_hf8(__m256h __A) |
|
_mm256_mask_cvtph_hf8
__m128i _mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) |
|
_mm256_maskz_cvtph_hf8
__m128i _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) |
|
_mm512_cvtph_hf8
__m256i _mm512_cvtph_hf8(__m512h __A) |
|
_mm512_mask_cvtph_hf8
__m256i _mm512_mask_cvtph_hf8(__m256i __W, __mmask32 __U, __m512h __A) |
|
_mm512_maskz_cvtph_hf8
__m256i _mm512_maskz_cvtph_hf8(__mmask32 __U, __m512h __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP8_CONVERT_128 | AVX10.2 or AVX10_V1_AUX | Nova Lake, Diamond Rapids |
AVX512_FP8_CONVERT_256 | AVX10.2 or AVX10_V1_AUX | Nova Lake, Diamond Rapids |
AVX512_FP8_CONVERT_512 | AVX10.2 or AVX10_V1_AUX | Nova Lake, Diamond Rapids |
More AVX10.2 instructions
- VADDBF16
- VCMPBF16
- VCOMISBF16
- VCOMXSD
- VCOMXSH
- VCOMXSS
- VCVT2PH2BF8
- VCVT2PH2BF8S
- VCVT2PH2HF8
- VCVT2PH2HF8S
- VCVT2PS2PHX
- VCVTBF162IBS
- VCVTBF162IUBS
- VCVTBIASPH2BF8
- VCVTBIASPH2BF8S
- VCVTBIASPH2HF8
- VCVTBIASPH2HF8S
- VCVTHF82PH
- VCVTPH2BF8
- VCVTPH2BF8S
- VCVTPH2HF8S
- VCVTPH2IBS
- VCVTPH2IUBS
- VCVTPS2IBS
- VCVTPS2IUBS
- VCVTTBF162IBS
- VCVTTBF162IUBS
- VCVTTPD2DQS
- VCVTTPD2QQS
- VCVTTPD2UDQS
- VCVTTPD2UQQS
- VCVTTPH2IBS
- VCVTTPH2IUBS
- VCVTTPS2DQS
- VCVTTPS2IBS
- VCVTTPS2IUBS
- VCVTTPS2QQS
- VCVTTPS2UDQS
- VCVTTPS2UQQS
- VCVTTSD2SIS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.