VCVTPH2HF8

VCVTPH2HF8 rounds each half-precision value to the 8-bit E4M3 format, which the mnemonics call HF8, to nearest even, and packs the bytes into the low half of the destination as VCVTPH2BF8 does for E5M2: the 32 halves of a zmm register give 32 bytes in a ymm register, and the bits above are cleared. It belongs to AVX10.2, opcode 18h with the F3 prefix in EVEX map 5, and takes a write mask with one bit per result byte and a broadcast half. TDPHF8PS describes the format: an exponent bias of 7, 448 as the largest value, and no infinity, only a NaN at 7Fh and FFh. VCVTHF82PH converts back, exactly.

Where the halves land#

E4M3 has 4 exponent bits to FP16’s 5 and 3 fraction bits to its 10, so both ends of the half range fall outside it. At the top, a half above 464, halfway from 448 to the 480 that the NaN’s encoding would otherwise hold, becomes the NaN with the half’s sign; 464 itself rounds to 448, whose fraction is the even one. An infinity and a NaN give the NaN as well. VCVTPH2HF8S gives 448 instead.

At the bottom, halves below 2^-6 become E4M3 denormals in steps of 2^-9, still rounded to nearest even, and a half of 2^-10 or less becomes a zero of its sign, which takes in every FP16 denormal. As an example, the half nearest 0.1 (2E66h) gives 1Dh, which is 0.1015625, and 1.0 gives 38h. DAZ and FTZ are not obeyed, MXCSR is neither read nor written, and no exception is raised.

In our builds#

GCC 14 rejects -mavx10.2. Clang 23 compiles _mm512_cvtph_hf8(a) to vcvtph2hf8 ymm0, zmm0, and _mm256_cvtph_hf8(a) to vcvtph2hf8 xmm0, ymm0 followed by VZEROUPPER. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        ymm1.hf8[i] = to_hf8(src2.f16[i])
    elif zeroing:
        ymm1.hf8[i] = 0
    # else: ymm1.hf8[i] keeps its value
for i in range(VL // 16, 16):
    ymm1.b[i] = 0
# m16bcst: src2.f16[i] is the m16 for every i
# HF8: to nearest even, denormals kept, no flags; MXCSR unused
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2HF8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions