VCVTPH2HF8S

VCVTPH2HF8S is VCVTPH2HF8 with saturation: a half above 464, which the plain form turns into E4M3’s NaN, gives 448 instead, the largest E4M3 value (7Eh, or FEh when negative). A NaN still gives the NaN, 7Fh or FFh by its sign. Everything else matches the plain form: rounding to nearest even whatever MXCSR says, denormal results kept, no flag and no exception. It is opcode 1Bh with the F3 prefix in EVEX map 5, next to the plain form’s 18h, and writes 8, 16 or 32 bytes into the low half of the destination, clearing the rest. VCVT2PH2HF8S converts two registers at once.

An infinite half#

E4M3 has no infinity, so the plain form maps an infinite half to the NaN. For this form the AVX10.2 specification gives two answers: its description of the instruction and its helper function saturate an infinity to 448 of the same sign, as the Operation block here does, while its Table 3.6 lists the NaN for infinity at the input of both E4M3 flavors.

In our builds#

GCC 14 rejects -mavx10.2. Clang 23 compiles _mm512_cvts_ph_hf8(a) to vcvtph2hf8s ymm0, zmm0; the _mm256_ and _mm_ forms write 16 and 8 bytes to an xmm register. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        ymm1.hf8[i] = to_hf8s(src2.f16[i])
    elif zeroing:
        ymm1.hf8[i] = 0
    # else: ymm1.hf8[i] keeps its value
for i in range(VL // 16, 16):
    ymm1.b[i] = 0
# m16bcst: src2.f16[i] is the m16 for every i
# HF8: to nearest even, denormals kept, no flags; MXCSR unused
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2HF8S, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS

All 96 AVX10.2 instructions