VCVTPH2IBS

VCVTPH2IBS converts each half-precision value to a signed byte, rounding as MXCSR.RC or the {er} operand says, and saturates: above 127 gives 7Fh, below -128 gives 80h, and a NaN gives 0. The byte lands in the low half of its 16-bit element and the high half is cleared, so the 32 halves of a zmm register give 32 bytes, one in every other byte; VPMOVWB packs them. Out-of-range values, infinities and NaNs set IE, and an inexact result in range sets PE. It is the half-precision member of the family that VCVTPS2IBS’s page describes: opcode 69h without a prefix in EVEX map 5, W0, with a write mask, a broadcast half and {er} on the 512-bit register form. VADDPH covers the format.

Halves and bytes#

A half has 11 significant bits, so every integer from -128 to 255 is exact in it, but its range reaches 65,504, so most halves are out of range for a byte. The specification’s helper function sets the range for each rounding mode: to nearest even, below -128.5 or from 127.5 on, so -128.5 rounds to -128 in range while 127.5 gives 7Fh with IE. VCVTPH2W converts to words instead and returns 8000h, the integer indefinite, for anything out of its range.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_ipcvts_ph_epi8 to vcvtph2ibs zmm0, zmm0. A loop that clamps _Float16 values to -128 and 127 and stores them as int8_t keeps VMAXPH, VMINPH and VCVTTPH2W, then packs with VPMOVWB and VPERMB. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.w[i] = cvts_int(a, 8) & 0xFF
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2IBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS

All 96 AVX10.2 instructions