VCVTPH2IUBS

VCVTPH2IUBS converts each half-precision value to an unsigned byte, rounding as MXCSR.RC or the {er} operand says: above 255 gives FFh, below 0 gives 0, and a NaN gives 0, each result in the low byte of its word with the high byte cleared. Its opcode is 6Bh without a prefix in EVEX map 5, two above the signed VCVTPH2IBS’s 69h, and the two pages share everything else; VCVTPS2IBS describes the family.

Where the range ends#

The rounding decides which values set IE. The specification’s helper function gives a range for each mode: to nearest even, below -1/2 or from 255.5 on; rounding down, anything below 0, so -0.1 sets IE and gives 0; rounding up, -1 or less, and anything above 255. A value that stays in range but is not an integer sets PE. The comment at the top of that helper gives the unsigned maximum as 2^(w-1), which would be 128 for a byte; its code returns FFh. The helper for the single-precision VCVTPS2IUBS has one range for every mode instead.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_ipcvts_ph_epu8 to vcvtph2iubs zmm0, zmm0, and _mm512_ipcvts_roundph_epu8(x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC) to vcvtph2iubs zmm0, zmm0, {rz-sae}, which gives the results of the truncating VCVTTPH2IUBS without reporting exceptions. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.w[i] = cvts_uint(a, 8)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2IUBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS

All 96 AVX10.2 instructions