x86-64.net

Instruction

VCVTPH2IUBS

Converts packed half-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 16-bit element.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTPH2IUBS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTPH2IUBS xmm {k}{z}, xmm VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512EVEX.128.NP.MAP5.W0 6B /rAVX10.2
VCVTPH2IUBS xmm {k}{z}, m128/m16bcst VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512EVEX.128.NP.MAP5.W0 6B /rAVX10.2
VCVTPH2IUBS ymm {k}{z}, ymm VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512EVEX.256.NP.MAP5.W0 6B /rAVX10.2
VCVTPH2IUBS ymm {k}{z}, m256/m16bcst VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512EVEX.256.NP.MAP5.W0 6B /rAVX10.2
VCVTPH2IUBS zmm {k}{z}, zmm, {er} VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512EVEX.512.NP.MAP5.W0 6B /rAVX10.2
VCVTPH2IUBS zmm {k}{z}, m512/m16bcst VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512EVEX.512.NP.MAP5.W0 6B /rAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2IUBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_ipcvts_ph_epu8 __m128i _mm_ipcvts_ph_epu8(__m128h A)

VCVTPH2IUBS xmm, xmm EVEX.128 -mavx10.2

VCVTPH2IUBS xmm, xmm EVEX.128 -mavx -mavx10.2with AVX enabled

_mm_mask_ipcvts_ph_epu8 __m128i _mm_mask_ipcvts_ph_epu8(__m128i W, __mmask8 U, __m128h A)

VCVTPH2IUBS xmm {k}, xmm EVEX.128 -mavx10.2

VCVTPH2IUBS xmm {k}, xmm EVEX.128 -mavx -mavx10.2with AVX enabled

_mm_maskz_ipcvts_ph_epu8 __m128i _mm_maskz_ipcvts_ph_epu8(__mmask8 U, __m128h A)

VCVTPH2IUBS xmm {k}{z}, xmm EVEX.128 -mavx10.2

VCVTPH2IUBS xmm {k}{z}, xmm EVEX.128 -mavx -mavx10.2with AVX enabled

_mm256_ipcvts_ph_epu8 __m256i _mm256_ipcvts_ph_epu8(__m256h A)

VCVTPH2IUBS ymm, ymm EVEX.256 -mavx10.2 -mavx

VCVTPH2IUBS ymm, ymm EVEX.256 -mavx -mavx10.2with AVX enabled

_mm256_mask_ipcvts_ph_epu8 __m256i _mm256_mask_ipcvts_ph_epu8(__m256i W, __mmask16 U, __m256h A)

VCVTPH2IUBS ymm {k}, ymm EVEX.256 -mavx10.2

VCVTPH2IUBS ymm {k}, ymm EVEX.256 -mavx -mavx10.2with AVX enabled

_mm256_maskz_ipcvts_ph_epu8 __m256i _mm256_maskz_ipcvts_ph_epu8(__mmask16 U, __m256h A)

VCVTPH2IUBS ymm {k}{z}, ymm EVEX.256 -mavx10.2 -mavx

VCVTPH2IUBS ymm {k}{z}, ymm EVEX.256 -mavx -mavx10.2with AVX enabled

_mm512_ipcvts_ph_epu8 __m512i _mm512_ipcvts_ph_epu8(__m512h A)

VCVTPH2IUBS zmm, zmm EVEX.512 -mavx10.2 -mavx512f

VCVTPH2IUBS zmm, zmm EVEX.512 -mavx -mavx10.2 -mavx512fwith AVX enabled

_mm512_ipcvts_roundph_epu8 __m512i _mm512_ipcvts_roundph_epu8(__m512h A, const int R)

VCVTPH2IUBS zmm, zmm, {er} EVEX.512 -mavx10.2 -mavx512f

VCVTPH2IUBS zmm, zmm, {er} EVEX.512 -mavx -mavx10.2 -mavx512fwith AVX enabled

_mm512_mask_ipcvts_ph_epu8 __m512i _mm512_mask_ipcvts_ph_epu8(__m512i W, __mmask32 U, __m512h A)

VCVTPH2IUBS zmm {k}, zmm EVEX.512 -mavx10.2

VCVTPH2IUBS zmm {k}, zmm EVEX.512 -mavx -mavx10.2with AVX enabled

_mm512_mask_ipcvts_roundph_epu8 __m512i _mm512_mask_ipcvts_roundph_epu8(__m512i W, __mmask32 U, __m512h A, const int R)

VCVTPH2IUBS zmm {k}, zmm, {er} EVEX.512 -mavx10.2

VCVTPH2IUBS zmm {k}, zmm, {er} EVEX.512 -mavx -mavx10.2with AVX enabled

_mm512_maskz_ipcvts_ph_epu8 __m512i _mm512_maskz_ipcvts_ph_epu8(__mmask32 U, __m512h A)

VCVTPH2IUBS zmm {k}{z}, zmm EVEX.512 -mavx10.2 -mavx512f

VCVTPH2IUBS zmm {k}{z}, zmm EVEX.512 -mavx -mavx10.2 -mavx512fwith AVX enabled

_mm512_maskz_ipcvts_roundph_epu8 __m512i _mm512_maskz_ipcvts_roundph_epu8(__mmask32 U, __m512h A, const int R)

VCVTPH2IUBS zmm {k}{z}, zmm, {er} EVEX.512 -mavx10.2 -mavx512f

VCVTPH2IUBS zmm {k}{z}, zmm, {er} EVEX.512 -mavx -mavx10.2 -mavx512fwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_SAT_CVT_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_SAT_CVT_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_SAT_CVT_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.