VCVTPH2PD

VCVTPH2PD widens half-precision values to doubles: two from the low 32 bits of the source into an xmm register, four from 64 bits into a ymm register, eight from 128 bits into a zmm register. Every half, denormals included, is exactly a double, so nothing is rounded and the result never depends on MXCSR.RC; Intel’s optimization manual notes that a denormal half becomes a normal value in the wider format (Section 18.5.7).

It came with AVX512-FP16 (CPUID leaf 7, EDX bit 23, with AVX512VL for the xmm and ymm forms) and is part of AVX10.1; VADDPH covers that extension. F16C, the older extension, has only VCVTPH2PS and its way back: before AVX512-FP16, a half reached double precision in two steps, through a single. The opcode is that of CVTPS2PD, 5Ah without a prefix, in EVEX map 5. The source is a quarter of the destination’s width: the zmm form reads an xmm register or 16 bytes of memory, the xmm form only 4 bytes, and one half from memory can be broadcast to every element.

Flags that differ from VCVTPH2PS#

Intel’s manual lists invalid and denormal as the exceptions VCVTPH2PD can report, as it does for VCVTPH2PSX, the AVX512-FP16 conversion to singles. For VCVTPH2PS, the F16C and AVX512F one, it states the opposite for denormals: no denormal exception, and MXCSR.DAZ ignored. A program that unmasks the denormal exception cannot count on the newer conversions behaving like VCVTPH2PS there; a signaling NaN sets the invalid flag in all of them. The zmm register form takes {sae}, which suppresses both flags and any #XM.

In compiled code#

With -march=sapphirerapids, Clang 23 at -O2 widens an array of _Float16 into an array of double with VCVTPH2PD from memory into ymm registers. GCC 14 at -O2 converts one element at a time with VCVTSH2SD when the count is known only at run time or leaves a remainder, as 1,001 does; for a constant count that fills whole vectors, such as 1,024, it vectorizes in two steps, VCVTPH2PSX and then VCVTPS2PD, over global arrays and through pointer parameters alike. At -O3 it takes those two steps for every count and finishes any remainder with VCVTSH2SD. Without AVX512-FP16, as with -march=znver5, Clang uses VCVTPH2PS and VCVTPS2PD, and GCC calls the library routine __extendhfdf2 for each element. Both routes give the same doubles, since the single in between is exact.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.f64[i] = to_f64(src2.f16[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Quarter); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS

All 686 AVX10.1 instructions