VCVTPH2PS

VCVTPH2PS widens half-precision values (IEEE 754’s binary16: a sign, 5 exponent bits and 10 fraction bits) to singles: four from the low 64 bits of an XMM register or from memory, or eight into a YMM register. Every half, denormals included, has an exact single, so nothing is rounded and the result never depends on MXCSR.RC. It came with F16C (CPUID.01H:ECX[29]), which has only this conversion and VCVTPS2PH back: on such processors halves are a storage format, widened before any arithmetic. Intel’s optimization manual weighs the memory and bandwidth such data saves against the cost of converting it (Section 15.14).

Denormals and NaNs#

Intel’s and AMD’s manuals both say that a denormal half converts to its normal single value with MXCSR.DAZ ignored and no denormal exception. AMD’s exception table for the instruction nonetheless lists the denormal flag, with overflow, underflow and precision. The cases recorded on Zen 5 follow the text: with DAZ set, the smallest denormal half 0001h became 2^-24 (33800000h), and no flag but IE was set. IE came from a signaling NaN, which the conversion makes quiet, keeping its payload in the top bits of the single’s.

In compiled code#

GCC 14 and Clang 23 at -O2 with -mf16c convert a _Float16 to float with VCVTPH2PS on the register; GCC first clears the rest of it with VPBLENDW, so the conversion sees zeros in the other elements. A loop widening an array of halves becomes the YMM form with a memory operand in Clang, as in the manual’s example (Example 15-33), while GCC converts one element at a time, inserting each half with VPINSRW. Adding two _Float16 values widens both, adds them with VADDSS and narrows the sum with VCVTPS2PH.

The EVEX forms (AVX-512F or AVX10.1) widen sixteen halves into a ZMM register, with masking and {sae}; VCVTPH2PSX of AVX512-FP16 adds broadcast. The instruction table of AMD’s Zen 5 guide gives the XMM form one macro-op with a latency of three cycles, and the YMM form from a register two macro-ops and four cycles.

In the optimization guide

What the optimization guide says about VCVTPH2PS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Zen and Zen+

• Vectors and floating point: Carry-less multiplication with PCLMULQDQ and the half-precision conversions VCVTPH2PS and VCVTPS2PH are microcoded, in AMD’s spreadsheet and in LLVM’s model.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = src2.f16[i]
        zmm1.f32[i] = to_f32_f16c(a)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-11

EVEX forms

AVX512-E11

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More F16C instructions

• VCVTPS2PH

More AVX10.1 instructions

• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI

All 686 AVX10.1 instructions