x86-64.net

Instruction

VCVTPH2PS

Converts packed half-precision values to singles, which is exact.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTPH2PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTPH2PS xmm, m64 VCVTPH2PS_XMMdq_MEMqVEX.128.66.0F38.W0 13 /rF16C
VCVTPH2PS xmm, xmm VCVTPH2PS_XMMdq_XMMqVEX.128.66.0F38.W0 13 /rF16C
VCVTPH2PS ymm, m128 VCVTPH2PS_YMMqq_MEMdqVEX.256.66.0F38.W0 13 /rF16C
VCVTPH2PS ymm, xmm VCVTPH2PS_YMMqq_XMMdqVEX.256.66.0F38.W0 13 /rF16C
VCVTPH2PS zmm {k}{z}, ymm, {sae} VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512EVEX.512.66.0F38.W0 13 /rAVX10.1 or AVX512F
VCVTPH2PS zmm {k}{z}, m256 VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512EVEX.512.66.0F38.W0 13 /rAVX10.1 or AVX512F
VCVTPH2PS xmm {k}{z}, xmm VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512EVEX.128.66.0F38.W0 13 /rAVX10.1 or AVX512F + AVX512VL
VCVTPH2PS xmm {k}{z}, m64 VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512EVEX.128.66.0F38.W0 13 /rAVX10.1 or AVX512F + AVX512VL
VCVTPH2PS ymm {k}{z}, xmm VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512EVEX.256.66.0F38.W0 13 /rAVX10.1 or AVX512F + AVX512VL
VCVTPH2PS ymm {k}{z}, m128 VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512EVEX.256.66.0F38.W0 13 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtph_ps __m128 _mm_cvtph_ps(__m128i __a)

VCVTPH2PS xmm, xmm VEX.128 -mf16c

_mm_mask_cvtph_ps __m128 _mm_mask_cvtph_ps(__m128 __W, __mmask8 __U, __m128i __A)

VCVTPH2PS xmm {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_cvtph_ps __m128 _mm_maskz_cvtph_ps(__mmask8 __U, __m128i __A)

VCVTPH2PS xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_cvtph_ps __m256 _mm256_cvtph_ps(__m128i __a)

VCVTPH2PS ymm, xmm VEX.256 -mf16c

_mm256_mask_cvtph_ps __m256 _mm256_mask_cvtph_ps(__m256 __W, __mmask8 __U, __m128i __A)

VCVTPH2PS ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_maskz_cvtph_ps __m256 _mm256_maskz_cvtph_ps(__mmask8 __U, __m128i __A)

VCVTPH2PS ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm512_cvt_roundph_ps __m512 _mm512_cvt_roundph_ps(__m256i A, const int R)

VCVTPH2PS zmm, ymm, {sae} EVEX.512 -mavx512f

_mm512_cvtph_ps __m512 _mm512_cvtph_ps(__m256i __A)

VCVTPH2PS zmm, ymm EVEX.512 -mavx512f

_mm512_mask_cvt_roundph_ps __m512 _mm512_mask_cvt_roundph_ps(__m512 W, __mmask16 U, __m256i A, const int R)

VCVTPH2PS zmm {k}, ymm, {sae} EVEX.512 -mavx512f

_mm512_mask_cvtph_ps __m512 _mm512_mask_cvtph_ps(__m512 __W, __mmask16 __U, __m256i __A)

VCVTPH2PS zmm {k}, ymm EVEX.512 -mavx512f

_mm512_maskz_cvt_roundph_ps __m512 _mm512_maskz_cvt_roundph_ps(__mmask16 U, __m256i A, const int R)

VCVTPH2PS zmm {k}{z}, ymm, {sae} EVEX.512 -mavx512f

_mm512_maskz_cvtph_ps __m512 _mm512_maskz_cvtph_ps(__mmask16 __U, __m256i __A)

VCVTPH2PS zmm {k}{z}, ymm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
F16C

F16C
CPUID.01H:ECX[29] F16C

Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2

Note: XED gives Bulldozer F16C; GCC enables it from -march=bdver2 (Piledriver) on.

AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.