VCVTPH2PSX

VCVTPH2PSX widens half-precision values to singles: four from 64 bits into an XMM register, eight into a YMM register and sixteen into a ZMM register. It does what VCVTPH2PS does, and shares its entry in Intel’s manual: every half, denormals included, is exactly a single, so nothing is rounded and MXCSR.RC plays no part. The new encoding, opcode 13h in EVEX map 6 with the 66 prefix, where the EVEX VCVTPH2PS has the same byte in 0F38, adds one thing: a source of one half broadcast from memory to every element ({1to16} and so on). Intel’s optimization manual recommends it over the older form for that reason (Sections 18.5.6 and 18.5.7). VADDPH covers AVX512-FP16 and the format.

A different exception list#

The shared entry gives VCVTPH2PSX the exceptions invalid and denormal, where VCVTPH2PS reports only invalid; the same entry says that for a denormal input VCVTPH2PS returns the normal result with DAZ ignored and no denormal exception. A program with the denormal exception unmasked can therefore see VCVTPH2PSX fault where VCVTPH2PS does not, as VCVTPH2PD’s page notes for the conversion to doubles. The 512-bit register form takes {sae}.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile f[i] = h[i], from a _Float16 array to a float array, to VCVTPH2PSX, never VCVTPH2PS: GCC from ymm to zmm registers after a load, Clang from memory into ymm registers. _mm512_cvtxph_ps gives it too; a single value is converted with VCVTSH2SS. Without AVX512-FP16 the same loop uses VCVTPH2PS, as its page shows. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPH2PSX.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.f32[i] = to_f32(src2.f16[i])
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2PSX, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD

All 686 AVX10.1 instructions