VCVTPH2QQ

VCVTPH2QQ converts halves to signed quadwords, rounding by MXCSR.RC or, on the 512-bit register form, by an {er} mode. The source is a quarter as wide as the destination: 8 halves from an XMM register or 16 bytes of memory fill a ZMM register, 4 fill a YMM register, and the XMM form reads only 32 bits for its 2 quadwords. The opcode is 7Bh with the 66 prefix in EVEX map 5, the byte of VCVTPS2QQ in the 0F map; VCVTTPH2QQ truncates and VCVTQQ2PH goes the other way.

Far more room than needed#

A finite half is an integer of at most 65504 in magnitude once rounded, so quadwords are 48 bits wider than any result needs; the same values fit VCVTPH2DQ, and the reason to use this form is a quadword layout, as for indexes or 64-bit sums. Intel’s entry lists invalid and precision: NaN and the infinities give the indefinite value 8000000000000000h with IE, and a dropped fraction sets PE. A half can be broadcast from memory, and a write mask merges or zeroes quadwords.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, _mm512_cvtph_epi64 gives vcvtph2qq zmm0, xmm0 and _mm_cvtph_epi64 the XMM form in GCC 14 and Clang 23. For a[i] = (int64_t)rintf(h[i]) with -fno-math-errno, Clang used VRNDSCALEPH and then the truncating VCVTTPH2QQ, four XMM results per pass, while GCC stayed scalar, with VCVTSH2SS and VCVTSS2SI per element. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPH2QQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = cvt_int(src2.f16[i], 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Quarter); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2QQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI

All 686 AVX10.1 instructions