VCVTPH2UDQ

VCVTPH2UDQ converts halves to unsigned doublewords: 4, 8 or 16 of them from the low 64, 128 or 256 bits of the source into an XMM, YMM or ZMM register, rounding by MXCSR.RC or by an {er} mode on the 512-bit register form. The opcode is 79h without a prefix in EVEX map 5, as VCVTPS2UDQ has it in the 0F map; the signed form is VCVTPH2DQ and the truncating one VCVTTPH2UDQ.

The negative side#

Any half from 0 to 65504 fits, so the only values out of range are NaN, the infinities and negative values that round to -1 or below: for those Intel’s entry raises the invalid exception and, when it is masked, returns FFFFFFFFh. A small negative value that rounds to zero, such as -0.25 in round to nearest, gives 0 and only the precision flag. Since the largest finite half is far below 2^32 - 1, FFFFFFFFh never stands for a converted number, unlike the singles’ VCVTPS2UDQ, where 4,294,967,040 and its neighbours come close.

In our builds#

The intrinsic _mm512_cvtph_epu32 gives vcvtph2udq zmm0, ymm0 in GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 -mavx512fp16. Neither compiler chose it for C code: with -fno-math-errno, u[i] = (uint32_t)rintf(h[i]) became VRNDSCALEPH and the truncating VCVTTPH2UDQ in Clang, and in GCC a widening to singles, VRNDSCALEPS and VCVTTPS2UDQ. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPH2UDQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f16[i]
        zmm1.d[i] = cvt_uint(a, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2UDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS

All 686 AVX10.1 instructions