VCVTPH2UQQ

VCVTPH2UQQ converts halves to unsigned quadwords: 2, 4 or 8 of them from the low 32, 64 or 128 bits of the source into an XMM, YMM or ZMM register, rounding by MXCSR.RC or by an {er} mode on the 512-bit register form. The opcode is 79h with the 66 prefix in EVEX map 5, as for VCVTPS2UQQ in the 0F map; without the prefix the same byte is VCVTPH2UDQ. It is the unsigned partner of VCVTPH2QQ, and VCVTTPH2UQQ truncates.

What can fail#

Every half from 0 to 65504 fits with plenty to spare, so only NaN, the infinities and negative values that round to -1 or below are out of range. For them Intel’s entry raises the invalid exception and, masked, returns FFFFFFFFFFFFFFFFh, a value no finite half could produce; -0.25 rounded to nearest gives 0 with only the precision flag. A half can be broadcast from memory, and a write mask merges or zeroes quadwords.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, _mm512_cvtph_epu64 gives vcvtph2uqq zmm0, xmm0 in GCC 14 and Clang 23. For u[i] = (uint64_t)rintf(h[i]) with -fno-math-errno, Clang rounds with VRNDSCALEPH and truncates with VCVTTPH2UQQ, while GCC widens to singles, rounds with VRNDSCALEPS and converts with VCVTTPS2UQQ. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPH2UQQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f16[i]
        zmm1.q[i] = cvt_uint(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Quarter); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2UQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI

All 686 AVX10.1 instructions