x86-64.net

Instruction

VCVTPH2UQQ

Converts packed half-precision values to unsigned quadwords, rounding as MXCSR or the instruction selects.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTPH2UQQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTPH2UQQ xmm {k}{z}, xmm VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512EVEX.128.66.MAP5.W0 79 /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTPH2UQQ xmm {k}{z}, m128/m16bcst VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512EVEX.128.66.MAP5.W0 79 /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTPH2UQQ ymm {k}{z}, xmm VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512EVEX.256.66.MAP5.W0 79 /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTPH2UQQ ymm {k}{z}, m256/m16bcst VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512EVEX.256.66.MAP5.W0 79 /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTPH2UQQ zmm {k}{z}, xmm, {er} VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512EVEX.512.66.MAP5.W0 79 /rAVX10.1 or AVX512_FP16
VCVTPH2UQQ zmm {k}{z}, m512/m16bcst VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512EVEX.512.66.MAP5.W0 79 /rAVX10.1 or AVX512_FP16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2UQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtph_epu64 __m128i _mm_cvtph_epu64(__m128h __A)

VCVTPH2UQQ xmm, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_mask_cvtph_epu64 __m128i _mm_mask_cvtph_epu64(__m128i __W, __mmask8 __U, __m128h __A)

VCVTPH2UQQ xmm {k}, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_maskz_cvtph_epu64 __m128i _mm_maskz_cvtph_epu64(__mmask8 __U, __m128h __A)

VCVTPH2UQQ xmm {k}{z}, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm256_cvtph_epu64 __m256i _mm256_cvtph_epu64(__m128h __A)

VCVTPH2UQQ ymm, xmm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_mask_cvtph_epu64 __m256i _mm256_mask_cvtph_epu64(__m256i __W, __mmask8 __U, __m128h __A)

VCVTPH2UQQ ymm {k}, xmm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_maskz_cvtph_epu64 __m256i _mm256_maskz_cvtph_epu64(__mmask8 __U, __m128h __A)

VCVTPH2UQQ ymm {k}{z}, xmm EVEX.256 -mavx512fp16 -mavx512vl

_mm512_cvt_roundph_epu64 __m512i _mm512_cvt_roundph_epu64(__m128h A, const int R)

VCVTPH2UQQ zmm, xmm, {er} EVEX.512 -mavx512fp16

_mm512_cvtph_epu64 __m512i _mm512_cvtph_epu64(__m128h __A)

VCVTPH2UQQ zmm, xmm EVEX.512 -mavx512fp16

_mm512_mask_cvt_roundph_epu64 __m512i _mm512_mask_cvt_roundph_epu64(__m512i W, __mmask8 U, __m128h A, const int R)

VCVTPH2UQQ zmm {k}, xmm, {er} EVEX.512 -mavx512fp16

_mm512_mask_cvtph_epu64 __m512i _mm512_mask_cvtph_epu64(__m512i __W, __mmask8 __U, __m128h __A)

VCVTPH2UQQ zmm {k}, xmm EVEX.512 -mavx512fp16

_mm512_maskz_cvt_roundph_epu64 __m512i _mm512_maskz_cvt_roundph_epu64(__mmask8 U, __m128h A, const int R)

VCVTPH2UQQ zmm {k}{z}, xmm, {er} EVEX.512 -mavx512fp16

_mm512_maskz_cvtph_epu64 __m512i _mm512_maskz_cvtph_epu64(__mmask8 __U, __m128h __A)

VCVTPH2UQQ zmm {k}{z}, xmm EVEX.512 -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.