VCVTPH2UW

VCVTPH2UW converts halves to unsigned words, element for element: 8, 16 or 32 at a time, rounding by MXCSR.RC or by an {er} mode on the 512-bit register form. The opcode is 7Dh without a prefix in EVEX map 5, the byte of VCVTPH2W, which has 66; VCVTTPH2UW truncates and VCVTUW2PH goes back.

Every non-negative half fits#

The largest finite half, 65504, is below 65535, so from 0 up nothing overflows: only NaN, the infinities and negative values that round to -1 or below raise the invalid exception and, masked, give FFFFh. That value is therefore never a converted number, since the halves next to it are 65504 and infinity. A negative value that rounds to zero, such as -0.25 in round to nearest, gives 0 and sets only the precision flag. A half can be broadcast from memory, and a write mask merges or zeroes words.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, _mm512_cvtph_epu16 gives vcvtph2uw zmm0, zmm0 in GCC 14 and Clang 23. For u[i] = (uint16_t)rintf(h[i]) with -fno-math-errno, Clang rounds with VRNDSCALEPH and truncates with VCVTTPH2UW, and GCC widens to singles, rounds, converts with VCVTTPS2DQ and packs the words with VPERMT2W. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPH2UW.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.w[i] = cvt_uint(a, 16)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2UW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD

All 686 AVX10.1 instructions