VCVTPH2W

VCVTPH2W converts halves to signed words, element for element: 8, 16 or 32 at a time, rounding by MXCSR.RC or by an {er} mode on the 512-bit register form. There is no single-precision counterpart, since no SSE or AVX conversion produces words; the opcode is 7Dh with the 66 prefix in EVEX map 5, the byte that with F3 is the way back, VCVTW2PH. VCVTTPH2W truncates, and Intel’s optimization manual lists _mm_cvtph_epi16 among the conversions from FP16 (Section 18.5.7).

A range smaller than the format’s#

A half reaches 65504, a word only 32767, so this is the one signed conversion from halves where finite values overflow: anything that rounds to 32768 or more, or below -32768, raises the invalid exception and, masked, gives the indefinite value 8000h. Unlike the doubleword and quadword forms, that value is ambiguous, because -32768 is a half and converts to 8000h without any flag. Below 32768 the halves are 16 apart, so 32752 is the largest positive half that fits. A half can be broadcast from memory, and a write mask merges or zeroes words.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, _mm512_cvtph_epi16 gives vcvtph2w zmm0, zmm0 in GCC 14 and Clang 23, and _mm512_cvt_roundph_epi16 with _MM_FROUND_TO_NEG_INF adds {rd-sae}. C code did not produce it: a[i] = (int16_t)rintf(h[i]) became VRNDSCALEPH and VCVTTPH2W in Clang, and a widening to singles, rounding and VCVTTPS2DQ in GCC, with the doublewords packed back with VPERMT2W. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPH2W.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.w[i] = cvt_int(src2.f16[i], 16)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPH2W, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH

All 686 AVX10.1 instructions