x86-64.net

Instruction

VCVTPS2BF8S

Converts packed single-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

VCVTPS2BF8S is VCVTPS2BF8 with saturation. It rounds each single to E5M2 in the same way, to nearest even whatever MXCSR says, with no flags and with denormal singles read as zeros, and packs the bytes into the low end of an xmm register under a write mask of one bit per byte. Where VCVTPS2BF8 gives infinity, from 61,440 up and for an infinite single, it gives the largest finite value, 57,344 (7Bh), with the single’s sign. A NaN still gives a quiet NaN. The encoding is opcode 3Bh instead of 39h, with the F3 prefix in EVEX map 5, W0, in AVX10_V2_AUX.

Infinity too

ACE’s table of saturation results and its pseudocode agree that an infinite single saturates as well, to 57,344 of its sign. AVX10.2’s specification is split on this point for its conversions from halves, as the page of VCVT2PH2BF8S describes. A 512-bit source of 16 singles fills a whole xmm register, and ACE has no form that narrows two sources into one register, as VCVT2PH2BF8S does for halves.

In our builds

GCC 14 and Clang 23 have no option for AVX10_V2_AUX: Clang 23’s assembler and GNU as 2.44 reject the mnemonic, and ACE’s intrinsic _mm512_cvtpss_bf8 is missing from Clang 23’s headers. This site’s recorded cases include none of VCVTPS2BF8S.

Forms

Every encoding of VCVTPS2BF8S that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTPS2BF8S xmm {k}{z}, xmm VCVTPS2BF8S_XMMbf8_MASKmskw_XMMf32_AVX512EVEX.128.F3.MAP5.W0 3B /rAVX10_V2_AUX + AVX10
VCVTPS2BF8S xmm {k}{z}, m128/m32bcst VCVTPS2BF8S_XMMbf8_MASKmskw_MEMf32_AVX512_VL128EVEX.128.F3.MAP5.W0 3B /rAVX10_V2_AUX + AVX10
VCVTPS2BF8S xmm {k}{z}, ymm VCVTPS2BF8S_XMMbf8_MASKmskw_YMMf32_AVX512EVEX.256.F3.MAP5.W0 3B /rAVX10_V2_AUX + AVX10
VCVTPS2BF8S xmm {k}{z}, m256/m32bcst VCVTPS2BF8S_XMMbf8_MASKmskw_MEMf32_AVX512_VL256EVEX.256.F3.MAP5.W0 3B /rAVX10_V2_AUX + AVX10
VCVTPS2BF8S xmm {k}{z}, zmm VCVTPS2BF8S_XMMbf8_MASKmskw_ZMMf32_AVX512EVEX.512.F3.MAP5.W0 3B /rAVX10_V2_AUX + AVX10
VCVTPS2BF8S xmm {k}{z}, m512/m32bcst VCVTPS2BF8S_XMMbf8_MASKmskw_MEMf32_AVX512_VL512EVEX.512.F3.MAP5.W0 3B /rAVX10_V2_AUX + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Narrow: each single becomes a byte, in the same order, at the low end of the result.
VCVTPS2BF8S: each element narrowedResult bytes 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.0123456789101112131415zmm2or m512a1111111111111110k1a0a1a2a3a4a5a6a7a8a9a10a11a12a13a15xmm1

Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 singles. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result bytes 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        xmm1.bf8[i] = to_bf8s(src2.f32[i])
    elif zeroing:
        xmm1.bf8[i] = 0
    # else: xmm1.bf8[i] keeps its value
for i in range(VL // 32, 16):
    xmm1.b[i] = 0
# m32bcst: src2.f32[i] is the m32 for every i
# BF8: to nearest even, denormals kept, no flags; MXCSR unused
# xmm1 is zeroed from bit 128 up

Not run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VCVTPS2BF8S xmm {k}{z}, xmm/m128/m32bcst VCVTPS2BF8S xmm {k}{z}, ymm/m256/m32bcst VCVTPS2BF8S xmm {k}{z}, zmm/m512/m32bcst
xmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms
write masking
Memory forms
embedded broadcast (tuple Full); memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX10_V2_AUX_128

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_256
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_512
Same as AVX10_V2_AUX_128None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More AVX10_V2_AUX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.